REF

REF

1

t

=

= 0.04 s

f

CDCM9102

www.ti.com

SCAS922

– FEBRUARY 2012

desired

be less than 9 pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is

particularly sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. It is

recommended that the designer extract the stray and parasitic capacitance from the printed circuit board design

unnecessary; however, it is recommended that pads be implemented to accommodate an external load capacitor

so that the ppm error can be minimized.

STARTUP TIME ESTIMATION

The CDCM9102 contains a low-noise clock generator that calibrates to an optimal operating point at device

power up. In order to ensure proper device operation, the oscillator must be stable prior to the low-noise clock

generator calibration procedure. Quartz-based oscillators can take up to 2 ms to stabilize; therefore it is

recommended that the application ensure that the RESET pin is de-asserted at least 5 ms after the power supply

has finished ramping. This can be accomplished by controlling the RESET pin directly, or by applying a 47-nF

capacitor to ground on the RESET pin (this provides a delay because the RESET pin includes a 150-k

Ω pullup

resistor.

The CDCM9102 startup time can be estimated based on parameters defined in Table 5 and graphically shown in

Figure 12.

Table 5. CDCM9102 Startup Time Dependencies

Parameter

Definition

Description

Formula / Method of Determination

The reciprocal of the applied reference

Reference clock period

frequency in seconds

Power-supply rise time to low limit of

Power-up time (low limit)

Time required for power supply to ramp to 2.27 V

power-on-reset trip point

Power supply rise time to high limit of

Power-up time (high limit)

Time required for power supply to ramp to 2.64 V

power-on-reset trip point

After POR releases, the Colpitts oscillator is

enabled. This start-up time is required for the

500

μs best case and 800 μs worst case (for a crystal

Reference start-up time

oscillator to generate the requisite signal

input)

levels for the delay block to be clocked by the

reference input.

Internal delay time generated from the

Delay time

reference clock. This delay provides time for

the reference oscillator to stabilize.

VCO calibration time generated from the

reference clock. This process selects the

VCO calibration time

operating point for the VCO based on the PLL

settings.

Time requried for PLL to lock within

±10 ppm

PLL lock time

The PLL settles in 12.5

μs

(1)

Copyright

© 2012, Texas Instruments Incorporated

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