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LTC3838

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OPERATION (Refer to Functional Diagram)

Main Control Loop

The LTC3838 is a controlled on-time, valley current mode

step-down DC/DC dual controller with two channels

operating out of phase. Each channel drives both main

and synchronous N-channel MOSFETs. The two channels

can be either configured to two independently regulated

outputs, or combined into a single output.

The top MOSFET is turned on for a time interval determined

by a one-shot timer. The duration of the one-shot timer is

controlled to maintain a fixed switching frequency. As the

top MOSFET is turned off, the bottom MOSFET is turned

on after a small delay. The delay, or dead time, is to avoid

both top and bottom MOSFETs being on at the same time,

causing shoot-through current from VIN directly to power

ground. The next switching cycle is initiated when the cur-

rent comparator, ICMP, senses that inductor current falls

below the trip level set by voltages at the ITH and VRNG

pins. The bottom MOSFET is turned off immediately and

the top MOSFET on again, restarting the one-shot timer

and repeating the cycle. In order to avoid shoot-through

current, there is also a small dead-time delay before the

top MOSFET turns on. At this moment, the inductor cur-

rent hits its “valley” and starts to rise again.

Inductor current is determined by sensing the voltage

between SENSE+ and SENSE–, either by using an explicit

resistor connected in series with the inductor or by implic-

itly sensing the inductor’s DC resistive (DCR) voltage drop

through an RC filter connected across the inductor. The

trip level of the current comparator, ICMP, is proportional

to the voltage at the ITH pin, with a zero-current threshold

corresponding to an ITH voltage of around 0.8V.

The error amplifier (EA) adjusts this ITH voltage by com-

paring the feedback signal to the internal 0.6V reference

voltage. On Channel 1, the difference amplifier (DIFFAMP)

converts the differential feedback signal (VOUTSENSE1+ –

VOUTSENSE1–) to a single-ended input for the EA; Channel 2

uses VFB2 directly with respect to SGND. Output voltage is

regulated so that the feedback voltage is equal to the internal

0.6V reference. If the load current increases/decreases, it

causes a momentary drop/rise in the differential feedback

voltage relative to the reference. The EA then moves ITH

voltage, or inductor valley current setpoint, higher/lower

until the average inductor current again matches the load

current, so that the output voltage comes back to the

regulated voltage.

The LTC3838 features a detect transient (DTR) pin to detect

“load-release”, or a transient where the load current sud-

denly drops, by monitoring the first derivative of the ITH

voltage. When detected, the bottom gate (BG) is turned

off and inductor current flows through the body diode

in the bottom MOSFET, allowing the SW node voltage to

drop below PGND by the body diode’s forward-conduction

voltage. This creates a more negative differential voltage

(VSW – VOUT) across the inductor, allowing the inductor

current to drop faster to zero, thus creating less overshoot

on VOUT. See Load-Release Transient Detection in Applica-

tions Information for details.

Differential Output Sensing

This dual controller’s first channel features differential

output voltage sensing. The output voltage is resistively

divided externally to create a feedback voltage for the con-

troller. The internal difference amplifier (DIFFAMP) senses

this feedback voltage with respect to the output’s remote

ground reference to create a differential feedback voltage.

This scheme eliminates any ground offsets between local

ground and remote output ground, resulting in a more

accurate output voltage. Channel 1 allows remote output

ground to deviate as much as ±500mV with respect to

local ground (SGND).

DRVCC/EXTVCC/INTVCC Power

DRVCC1,2 are the power for the bottom MOSFET drivers.

Normally the two DRVCC pins are shorted together on

the PCB, and decoupled to PGND with a minimum 4.7μF

ceramic capacitor, CDRVCC. The top MOSFET drivers are

biased from the floating bootstrap capacitors (CB1,2)

which are recharged during each cycle through an external

Schottky diode when the top MOSFET turns off and the

SW pin swings down.

The DRVCC can be powered on two ways: an internal low-

dropout (LDO) linear voltage regulator that is powered

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