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LTC3838

3838fa

APPLICATIONS INFORMATION

In continuous mode operation, the minimum on-time limit

imposes a minimum duty cycle of:

DMIN = f • tON(MIN)

where tON(MIN) is the effective minimum on-time for the

switching regulator. As the equation shows, reducing the

operating frequency will alleviate the minimum duty cycle

constraint. If the minimum on-time that LTC3838 can

provide is longer than the on-time required by the duty

cycle to maintain the switching frequency, the switching

frequency will have to decrease to maintain the duty cycle,

but the output voltage will still remain in regulation. This is

generally more preferable to skipping cycles and causing

larger ripple at the output, which is typically seen in fixed

frequency switching regulators.

The tON(MIN) curves in the Typical Performance Charac-

teristics are measured with minimum load on TG and

BG, at extreme cases of VIN = 38V, and/or VOUT = 0.6V,

and/or programmed f = 2MHz (i.e., RT = 18k). In applica-

tions with different VIN, VOUT and/or f, the tON(MIN) that

can be achieved will generally be larger. Also, to guarantee

frequency and phase locking at light load, sufficient margin

needs to be added to account for the dead times (tD(TG/BG)

+ tD(TG/BG) in the Electrical Characteristics).

For applications that require relatively low on-time, proper

caution has to be taken when choosing the power MOSFET.

If the gate of the MOSFET is not able to fully turn on due

to insufficient on-time, there could be significant heat dis-

sipation and efficiency loss as a result of larger RDS(ON).

This may even cause early failure of the power MOSFET.

The minimum off-time is the smallest duration of time

that the TG pin can be turned low and then immediately

turned back high. This minimum off-time includes the

time to turn on the BG (bottom gate) and turn it back off,

plus the dead-time delays from TG off to BG on and from

BG off to TG on. The minimum off-time that the LTC3838

can achieve is 90ns.

The effective minimum off-time of the switching regulator,

or the shortest period of time that the SW node can stay

low, can be different from this minimum off-time. The main

factor impacting the effective minimum off-time is the top

and bottom power MOSFETs’ electrical characteristics,

such as Qg and turn-on/off delays. These characteristics

can either extend or shorten the SW nodes’ effective

minimum off-time. Large size (high Qg) power MOSFETs

generally tend to increase the effective minimum off-time

due to longer gate charging and discharging times. On

the other hand, imbalances in turn-on and turn-off delays

could reduce the effective minimum off-time.

The minimum off-time limit imposes a maximum duty

cycle of:

DMAX = 1 – f • tOFF(MIN)

where tOFF(MIN) is the effective minimum off-time of the

switching regulator. Reducing the operating frequency can

alleviate the maximum duty cycle constraint.

Figure 11. Light Loading On-Time Extension for Forced

Continuous Mode Operation

DEAD-TIME

DELAYS

NEGATIVE

INDUCTOR

CURRENT

IN FCM

DURING BG-TG DEAD TIME,

NEGATIVE INDUCTOR CURRENT

WILL FLOW THROUGH TOP MOSFET’S

BODY DIODE TO PRECHARGE SW NODE

3838 F11

TG-SW

(VGS OF TOP

MOSFET)

(VGS OF

BOTTOM

MOSFET)

VIN

–

VIN

DURING TG-BG DEAD TIME,

THE RATE OF SW NODE DISCHARGE

WILL DEPEND ON THE CAPACITANCE

ON THE SW NODE AND INDUCTOR

CURRENT MAGNITUDE

TOTAL CAPACITANCE

ON THE SW NODE

LTC3829 Datasheet(PDF) 33 Page - Linear Technology

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