LT1640AL datasheet(19/36 Pages) LINER

19 / 36 page

LTC4252-1/LTC4252-2

LTC4252A-1/LTC4252A-2

425212fd

APPLICATIONS INFORMATION

A low impedance short on one card may influence the

behavior of others sharing the same backplane. The initial

glitch and backplane sag as seen in Figure 6 Trace 1, can

rob charge from output capacitors on adjacent cards.

When the faulty card shuts down, current flows in to

refresh the capacitors. If LTC4252s are used by the other

cards, they respond by limiting the inrush current to a

value of 100mV/RS. If CT is sized correctly, the capacitors

will recharge long before CT times out.

POWER GOOD, PWRGD

PWRGD latches low if GATE charges up to within 2.8V of

VIN and DRAIN pulls below VDRNL during start-up. PWRGD

is reset in UVLO, in a UV condition or if CT charges up

to 4V. An overvoltage condition has no effect on PWRGD

status. A 58μA current pulls this pin high during reset.

Due to voltage transients between the power module and

PWRGD,optoisolationisrecommended.Thispinprovides

sufficent drive for an optocoupler. Figure 19 shows an

alternative NPN configuration with a limiting base resistor

for the PWRGD interface. The module enable input should

have protection from the negative input current.

MOSFET SELECTION

The external MOSFET switch must have adequate safe

operating area (SOA) to handle short-circuit conditions

until TIMER times out. These considerations take prece-

dence over DC current ratings. A MOSFET with adequate

SOA for a given application can always handle the required

current, but the opposite may not be true. Consult the

manufacturer’s MOSFET data sheet for safe operating

area and effective transient thermal impedance curves.

MOSFET selection is a 3-step process by assuming the

absense of a soft-start capacitor. First, RS is calculated

and then the time required to charge the load capacitance

is determined. This timing, along with the maximum

short-circuit current and maximum input voltage defines

an operating point that is checked against the MOSFET’s

SOA curve.

To begin a design, first specify the required load current

and Ioad capacitance, IL and CL. The circuit breaker cur-

rent trip point (VCB/RS) should be set to accommodate

the maximum load current. Note that maximum input

current to a DC/DC converter is expected at VSUPPLY(MIN).

RS is given by:

RS =

VCB(MIN)

IL(MAX)

(8)

where VCB(MIN) = 40mV (45mV for LTC4252A) represents

the guaranteed minimum circuit breaker threshold.

During the initial charging process, the LTC4252 may oper-

ate the MOSFET in current limit, forcing (VACL) between

80mV to 120mV (VACL is 54mV to 66mV for LTC4252A)

across RS. The minimum inrush current is given by:

IINRUSH(MIN)=

80mV

(9)

Maximum short-circuit current limit is calculated using

the maximum VACL. This gives

ISHORTCIRCUIT(MAX)=

120mV

(10)

The TIMER capacitor CT must be selected based on the

slowest expected charging rate; otherwise TIMER might

time out before the load capacitor is fully charged. A value

for CT is calculated based on the maximum time it takes

the load capacitor to charge. That time is given by:

tCL(CHARGE) =

C• V

CL •VSUPPLY(MAX)

IINRUSH(MIN)

(11)

The maximum current flowing in the DRAIN pin is given by:

IDRN(MAX) =

V SUPPLY(MAX)–VDRNCL

(12)

LT1640AL Datasheet(PDF) 19 Page - Linear Technology

LT1640AL Datasheet(HTML) 19 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL