| Electronic Components Datasheet Search |
|
LT1640AL Datasheet(PDF) 29 Page - Linear Technology |
|
|
|||||||||||||||||||||||||||||
LT1640AL Datasheet(HTML) 29 Page - Linear Technology |
|
29 / 36 page ![]() LTC4252-1/LTC4252-2 LTC4252A-1/LTC4252A-2 29 425212fd APPLICATIONS INFORMATION current begins to decline below VACL(t). The current limit loop shuts off and GATE releases at time point 8. At time point 9, the SENSE voltage falls below VCB and TIMER deactivates. Large values of CSS can cause premature circuit breaker time out as VACL(t) may exceed the VCB potential during the circuit breaker delay. The load capacitor is unable to achieve full charge in one GATE start-up cycle. A more serious side effect of large CSS values is SOA duration may be exceeded during soft-start into a low impedance load. A soft-start voltage below VCB will not activate the circuit breaker TIMER. Power Limit Circuit Breaker Figure 19 shows the LTC4252A-1 in a power limit circuit breaking application. The SENSE pin is modulated by the board supply voltage, VSUPPLY. The D1 Zener voltage, VZ is set to be the same as the low supply operating voltage, VSUPPLY(MIN) = 43V. If the goal is to have the high supply operating voltage, VSUPPLY(MAX) = 71V giving the same power at VSUPPLY(MIN), then resistors R4 and R6 are selected using the ratio: R6 R4 = VCB VSUPPLY(MAX) (16) If R6 is 27Ω, R4 is 38.3k. The peak circuit breaker power limit is: POWERMAX = VSUPPLY(MIN) +VSUPPLY(MAX) ()2 4• VSUPPLY(MIN) •VSUPPLY(MAX) •POWERSUPPLY(MIN) =1.064 •POWERSUPPLY(MIN) (17) when VSUPPLY = 0.5 • (VSUPPLY(MIN) + VSUPPLY(MAX)) = 57V. The peak power at the fault current limit occurs at the supply overvoltage threshold. The fault current limited power is: POWERFAULT = VSUPPLY RS •VACL –VSUPPLY –VZ ()•R6 R4 ⎛ ⎝⎜ ⎞ ⎠⎟ (18) TIMER GATE SENSE SS DRAIN VTMRH VDRNCL VACL VCB VDRNL VGS(th) VIN – VGATEH VTMRL 425212 F18 PWRGD 5.8μA 58μA 58μA TIMER GATE SENSE SS DRAIN VTMRH VDRNCL VCB VACL VDRNL VGS(th) VIN – VGATEH VTMRL PWRGD 5.8μA 58μA 58μA 12 34 567 7a 8 9 10 11 END OF INTIAL TIMING CYCLE 12 3 4 5 6 7 8 9 10 11 END OF INTIAL TIMING CYCLE OS CB + VOS) ACL + VOS) OS CB + VOS) ACL + VOS) DRN DRN Figure 18. Soft-Start Timing (All Waveforms Are Referenced to VEE) (18a) Without External CSS (18b) With External CSS |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |