MC34708 datasheet(31/159 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

MC34708

Functional Block Description

7.4

Interrupt Management

7.4.1

Control

The system is informed about important events, based on interrupts. Unmasked interrupt events are signaled to the processor

by driving the INT pin high; this is true whether the communication interface is configured for SPI or I2C.

Each interrupt is latched so that even if the interrupt source becomes inactive, the interrupt will remain set until cleared. Each

interrupt can be cleared by writing a 1 to the appropriate bit in the Interrupt Status register, which will also cause the interrupt line

to go low. If a new interrupt occurs while the processor clears an existing interrupt bit, the interrupt line will remain high.

Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high,

the interrupt line will not go high. A masked interrupt can still be read from the Interrupt Status register. This gives the processor

the option of polling for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the

device to determine if any interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked

interrupt bit was already high, the interrupt line will go high after unmasking.

The sense registers contain status and input sense bits, so the system processor can poll the current state of interrupt sources.

They are read only, and not latched or clearable.

Interrupts generated by external events are debounced. Therefore, the event needs to be stable throughout the debounce period

before an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary table following

later in this section. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.

Table 19. Coin Cell Voltage Specifications

VCOIN[2:0]

Output Voltage

000

2.50

001

2.70

010

2.80

011

2.90

100

3.00

101

3.10

110

3.20

111

3.30

Table 20. Coin Cell Electrical Specifications

Characteristics noted under conditions BP = 3.6 V, VBUS = 5.0 V, -40 C  TA  85 C, unless otherwise noted. Typical values

at BP = 3.6 V and TA = 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit

Notes

COIN CELL CHARGER

VLICELLACC Voltage Accuracy

100

ILICELLON

Coin Cell Charge Current in On and Watchdog modes ICOINHI

A

ILICELLOFF Coin Cell Charge Current in Off, cold start/warm start, and Low Power Off

modes (User Off / Memory Hold) ICOINLO

A

ILICELACC

Current Accuracy

COLICELL

LICELL Bypass Capacitor

100

LICELL Bypass Capacitor as coin cell replacement

4.7

F

MC34708 Datasheet(PDF) 31 Page - Freescale Semiconductor, Inc

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