Current Sharing Layout

LAYER A

MASTER

SLAVE

1

1

LAYER B

MASTER

SLAVE

1

1

UDG-07107

AGND

Prebias Startup Capability

PTH08T255W

pins of both modules are connected together to power the load. The GND pins of both modules are connected

via the GND plane. Four other inter-connection pins are connected between the modules. Figure 22 shows the

required layout of the inter-connection pins for two modules configured to share current. Notice that the Share

(pin 2) connection is routed between the Comp (pin 3) and CLKIO (pin 5) connections. AGND (pin 4) should be

connected as a thicker trace on an adjacent layer, running parallel to pins 2, 3 and 5. AGND must not be

connected to the GND plane.

Figure 22. Recommended Layout of Inter-Connection Pins Between Two Current Sharing Modules

A prebias startup condition occurs as a result of an external voltage being present at the output of a power

module prior to its output becoming active. This often occurs in complex digital systems when current from

another power source is backfed through a dual-supply logic component, such as an FPGA or ASIC. Another

path might be via clamp diodes as part of a dual-supply power-up sequencing arrangement. A prebias can cause

problems with power modules that incorporate synchronous rectifiers. This is because under most operating

conditions, these types of modules can sink as well as source output current.

or whenever the Inhibit pin is held low. However, to ensure satisfactory operation of this function, certain

voltage rises above the voltage backfed through the intrinsic diodes.

Copyright © 2008, Texas Instruments Incorporated

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