TMDS461 datasheet(21/43 Pages) TI1

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VCC

50 W

D+

D-

VD+ VID

50 W

VD-

-V

=(V

+V )

D+

D-

ICM

D+

D-

=V -V

=(V +V )

0.5pF

50 W

AVCC

TMDS461

www.ti.com ............................................................................................................................................................................................... SLLS915 – JANUARY 2009

SWITCHING CHARACTERISTICS (continued)

over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP(1)

MAX

UNIT

tJITC(PP)

Peak-to-peak output residual clock jitter

AVCC = 3.3 V, RT = 50 Ω, input TMDS clock

frequency = 225 MHz. See Figure 18 for

measurement setup; residual jitter is the total

jitter measured at TTP4 minus the jitter

measured at TTP1. See Figure 19 for the loss

profile of the cable used for tJITC(PP)

measurement.

tCLK1

Valid clock-detect enable time

AVCC = 3.3 V, RT = 50 Ω, input TMDS clock

300

500

frequency = 300 MHz. See Figure 17.

tCLK2

Invalid clock-detect disable time

AVCC = 3.3 V, RT = 50 Ω, input TMDS clock

500

800

frequency = 1 MHz. See Figure 17.

tSEL1

Port selection time (see (4)

AVCC = 3.3 V, RT = 50 Ω

300

500

tSEL2

Port deselection time (see (5))

AVCC = 3.3 V, RT = 50 Ω

fCD

Clock-detect frequency

AVCC = 3.3 V, RT = 50 Ω. See Figure 17.

300

MHz

(4)

tSEL1 includes the time for the valid clock detect enable time and tS1(HPD), because the tS1(HPD) event happens in parallel with tSEL1; thus,

the tSEL1 time is primarily the tCLK1 time.

(5)

tSEL2 is primarily the tS2(HPD) time.

Figure 13. TMDS Main Link Test Circuit

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