SN65MLVD040

SLLS902 – FEBRUARY 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION CONTINUED

The driver logic inputs and the receiver logic outputs are on separate pins rather than tied together as in some

transceiver designs. The drivers have separate enables (DE) and so does the receivers (RE). This arrangement

of separate logic inputs, logic outputs, and enable pins allows for a listen-while-talking operation. The devices are

characterized for operation from –40°C to 85°C.

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

1D–4D

35, 32, 28, 25

I

Data inputs for drivers

1R–4R

36, 33, 29, 26

O

Data output for receivers

1A–4A

47, 3, 9, 13

Bus I/O

M-LVDS bus non-inverting input/output

1B–4B

48, 4, 10, 14

Bus I/O

M-LVDS bus inverting input/output

6, 7, 18, 23, 27, 31, 34, 38,

GND

Circuit ground. ALL GND pins must be connected to ground.

43

2, 11, 15, 16, 24, 37, 45,

Supply voltage. ALL VCC pins must be connected to supply.

46

Receiver enable, active low, enable individual receivers. When this pin is left

1RE–4RE

40, 42, 19, 21

I

floating, internally this pin will be pulled to logic HIGH.

Driver enable, active high, individual enables the drivers. When this pin is left

1DE–4DE

1, 5, 8, 12

I

floating, internally this pin will be pulled to logic LOW.

Failsafe enable pin. When this pin is left floating, internally this pin will be

pulled to logic HIGH.

This pin enables the Type 2 receiver for the respective channel.

1FSEN–4FSEN

39, 41, 20, 22

I

xFSEN = L

→ Type 1 receiver inputs

xFSEN = H

→ Type 2 receiver inputs

Power Down pin. When this pin is left floating, internally this pin will be pulled

to logic LOW.

PDN

30

I

When PDN is HIGH, the device is powered up.

When PDN is LOW, the device overrides all other control and powers down. All

outputs are Hi-Z.

NC

17

Not Connected

NC

44

Not Connected. Internal TI Test pin. This pin must be left unconnected.

PowerPAD™

–

Connected to GND

2

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