A

B

1.62 k

Ω , ±1%

tc(n)

1/f0

0 V

0 V

Period Jitter

0 V

Peak to Peak Jitter

1/f0

PRBS INPUT

OUTPUT

CLOCK

INPUT

IDEAL

OUTPUT

ACTUAL

OUTPUT

0 V

0 V

Cycle to Cycle Jitter

0 V

OUTPUT

SN65MLVD040

www.ti.com

SLLS902 – FEBRUARY 2010

PARAMETER MEASUREMENT INFORMATION (continued)

Figure 7. Maximum Steady State Output Voltage

A.

All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A.

B.

The cycle-to-cycle measurement is made on a TEK TDS6604 running TDSJIT3 application software.

C.

All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer.

D.

Period jitter and cycle-to-cycle jitter are measured using a 125 MHz 50 ±1% duty cycle clock input. Measured over

75K samples.

E.

Figure 8. Driver Jitter Measurement Waveforms

Copyright © 2010, Texas Instruments Incorporated

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