MainSystemClock

MLVD206

1Tx1Rx

NumberofModules

Modules1

ModulesN

Centralized-SynchronousMainSystemClockM-LVDSDifferentialBus

Data/ControlM-LVDSDifferentialBus#1~#15

80~100

R

Source-SynchronousSubsystemClockM-LVDSDifferentialBus

M-LVDSBackplane

tsk(flight)BP

tsk(pp)DRVR

tsk(pp)RCVR

MLVD206

1Tx1Rx

MLVD206

1Tx1Rx

Timing

Process

Unit

Timing

Process

Unit

DataProcessUnit

ASIC/FPGA

uController

DataProcessUnit

ASIC/FPGA

uController

Subsystem

Clock

Subsystem

Clock

1DataWidth15

1DataWidth15

MLVD040(x2)

4Tx4Rx

MLVD040(x2)

4Tx4Rx

tsk(o)Source

80~100

R

80~100

R

80~100

R

80~100

R

80~100

R

SN65MLVD040

SLLS902 – FEBRUARY 2010

www.ti.com

APPLICATION INFORMATION

Source Synchronous System Clock (SSSC)

There are two approaches to transmit data in a synchronous system: centralized synchronous system clock

(CSSC) and source synchronous system clock (SSSC). CSSC systems synchronize data transmission between

different modules using a clock signal from a centralized source. The key requirement for a CSSC system is for

data transmission and reception to complete during a single clock cycle. The maximum operating frequency is

the inverse of the shortest clock cycle for which valid data transmission and reception can be ensured. SSSC

systems achieve higher operating frequencies by sending clock and data signals together to eliminate the flight

time on the transmission media, backplane, or cables. In SSSC systems, the maximum operating frequency is

limited by the cumulated skews that can exist between clock and data. The absolute flight time of data on the

backplane does not provide a limitation on the operating frequency as it does with CSSC.

The SN65MLVD082 can be designed for interfacing the data and clock to support source synchronous system

clock (SSSC) operation. It is specified for transmitting data up to 250 Mbps and clock frequencies up to 125

MHz. Figure 35 shows an example of a SSSC architecture supported by M-LVDS transceivers. The

SN65MLVD206, a single channel transceiver, transmits the main system clock between modules. A retiming unit

is then applied to the main system clock to generate a local clock for subsystem synchronization processing.

System operating data (or control) and subsystem clock signals are generated from the data processing unit,

such as a microprocessor, FPGA, or ASIC, on module 1, and sent to slave modules through the SN65MLVD082.

Such design configurations are common while transmitting parallel control data over the backplane with a higher

SSSC subsystem clock frequency. The subsystem clock frequency is aligned with the operating frequencies of

the data processing unit to synchronize data transmission between different units.

Figure 35. Using Differential M-LVDS to Perform Source Synchronous System Clock Distribution

22

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