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TPS65166 Datasheet(PDF) 17 Page - Texas Instruments |
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TPS65166 Datasheet(HTML) 17 Page - Texas Instruments |
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17 / 41 page ![]() Start-Up Sequencing EN2 Vlogic VOFFE EN1 VIN VS VONE PG VSS GD GDok DLY1 DLY2 DLY2 DLY2<DLY1 DLY2>DLY1 PowerGoodfor ScanDriveIC Power Good Output TPS65166 www.ti.com.......................................................................................................................................................................................... SLVS976 – SEPTEMBER 2009 The buck converter detects a short circuit if FB2 falls below 400 mV and the whole device except the buck converter itself is shut down as if EN2 would be disabled. The switching frequency of the buck converter is reduced to 1/4th of the normal operation frequency. If the short is removed the buck converter will start operation again and the whole device auto recovers to normal operation by doing startup sequencing as if EN2 would be enabled. The negative buck boost converter VOFFE has a short circuit protection where the switch current is limited to typically 300 mA and switching frequency is reduced to about 150 kHz. A short is detected if VOFFE rises above -3 V. The shunt regulator Vss has no short circuit protection. The device has adjustable start-up sequencing to provide correct sequencing as required by the display. Figure 23. Power Up Sequencing EN1 enables the buck converter. EN2 enables the negative buck boost converter VOFFE and Vss at the same time. DLY1 sets the delay time for the boost converter Vs and DLY2 sets the delay time for VONE. VONE does not start until DLY1 is elapsed. For simultaneous startup of Vs and VONE, DLY2 should be set to 0 by not connecting the DLY2 pin. Once VS and VONE are in regulation, PG goes high impedance to enable the scan driver IC. The power good output PG is an open drain output with typically 450 Ω resistance and requires a pull-up resistor to the 3.3V rail. The power good goes high impedance when the Vs and VONE voltage rails are in regulation and provides an enable signal for the external scan driver IC. Once power good is high impedance, the signal is latched until Vs or VONE detect a short circuit. The resulting maximum PG voltage if PG is low is dependent on R22 connection voltage (Vlogic) and R22 value. To calculate maximum resulting PG voltage for power bad signal use following formula: Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Link(s): TPS65166 |
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