TLK3104SCGNT

3.125Gbps QUAD SERIAL BACKPLANE TRANSCEIVER

SLLS537A − SEPTEMBER 2002 − REVISED JANUARY 2007

21

POST OFFICE BOX 655303

MDIO/MDC management interface (continued)

The MDIO management interface consists of a bidirectional data path (MDIO) and a clock reference (MDC).

The timing required to read to the internal registers is shown in Figure 14. The timing required to write from the

internal registers is shown in Figure 15. The TLK3104SCGNT reads in and latches out register bits on the rising

edge of the MDC clock and it could run as fast as 10 MHz. The MDIO controller, on the other hand, drives and

reads MDIO on falling edge of the MDC clock.

MDC

A4

MDIO

A0

R4

R0

0

1

1

0

0

High-Z

D15

D0

32 “1”s

Preamble

SFD

Read Code

PHY Address

Turn Around

Register Address

Data

Idle

Figure 14. Management Interface Read Timing

MDC

A4

MDIO

A0

R4

R0

1

0

1

0

0

D15

D0

32 “1”s

Preamble

SFD

Write Code

PHY Address

Turn Around

Register Address

Data

Idle

1

Figure 15. Management Interface Write Timing

The MDIO management interface allows up to 32 (16 bit) internal registers. Sixteen registers are defined by the

IEEE 802.3 clause 22 specification. Additional registers are allowed for expanded functionality. The

TLK3104SCGNT implements five IEEE defined registers. The TLK3104SCGNT also implements eight registers

for expanded functionality. Both the IEEE defined registers and the expanded functionality registers are outlined

in Table 6.

Table 6. MDIO Registers

REGISTER ADDRESS

REGISTER NAME

DEFINITION

0

Control

IEEE 802.3 defined. See Table 7

1

Status

IEEE 802.3 defined. See Table 8

2,3

PHY identifier

IEEE 802.3 defined. See Table 9

4−14

Not applicable

15

Extended status

IEEE 802.3 defined. See Table 10

16

Global configuration

See Table 11

17:20

Channel A−D configuration

See Tables 12, 13, 14, and 15

21

Test register

For production test only.

22

Channel status

See Table 16

23

Parity error detection

See Table 17

24

Channel synchronization FIFO

See Table 18