TLK3104SC datasheet(7/39 Pages) TI1

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TLK3104SCGNT

3.125Gbps QUAD SERIAL BACKPLANE TRANSCEIVER

SLLS537A − SEPTEMBER 2002 − REVISED JANUARY 2007

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

I/O

DESCRIPTION

JTAG Interface

TCLK

TTL input

JTAG clock. TCLK is used to clock state information and test data into and out of the device

during the operation of the test port.

TDI

TTL input

(with pullup)

JTAG input data. TDI is used to serially shift test data and test instructions into the device

during the operation of the test port.

TDO

TTL output

JTAG output data. TDO is used to serially shift test data and test instructions out of the device

during operation of the test port.

TMS

TTL input

(with pullup)

JTAG mode select. TMS is used to control the state of the internal test-port controller.

TRSTN

TTL input

(with pullup)

JTAG reset. TRSTN is used to reset the internal JTAG controller.

Management Data Interface

DVAD(0−4)

R1, T1,

T3, T2, R2

TTL input

Management address

MDC

TTL input

Management interface clock. MDC is the clock reference for the transfer of management

data to and from the protocol device.

MDIO

TTL I/O

Management address/data I/O. MDIO is the bidirectional serial data path for the transfer of

management data to and from the protocol device.

Control Pins

CODE

TTL input

(with pullup)

8-b/10-b enable. When this pin is asserted high, the on chip 8-b/10-b encoder/decoder is

enabled. For testing purpose, the 8-b/10-b endec could be bypassed by driving the pin low. If

intended to use bypass mode under normal operation, an 8-b/10-b or equivalent coding

scheme is needed to encode the random data before it enters the TLK3104SCGNT.

CONFIG0,

CONFIG1

D2, C2

TTL input

(with pulldown)

Configuration pins. Put the device under one of the four operation modes: TX only, RX only,

transceiver, and repeater mode.

ENABLE

TTL Input (with

pullup)

Standby enable. When this pin is held low, the device is disabled for IDDQ testing. When

high, the device operates normally.

LPEN(A−D)

C3, D3,

P3, R3

TTL input

(with pulldown)

Internal loop enable, channels A−D. When high, the serial output for each channel is

internally looped back to its serial input.

PRBSEN

TTL input

(with pulldown)

PRBS testing enable. When this pin is asserted high, the device is put into the PRBS testing

mode.

PSYNC

TTL input (with

pulldown)

Channel synchronization enable. When PSYNC = high, the channel synchronization FIFO

at the receive data path is enabled. All four channels are clocked by RCA.

RSTN

TTL input (with

pullup)

Chip reset. Pulsing this pin low for at least 8 RFC cycles resets the logic states for the whole

chip.

SYNCEN

TTL input

(with pullup)

Comma detect enable. When this pin is asserted high, the comma detect circuit for byte

alignment is turned on.

TESTEN

TTL input

(with pulldown)

Test mode enable should be left unconnected or tied low. This is for production test only.

TLK3104SC Datasheet(PDF) 7 Page - Texas Instruments

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