TLK3104SCGNT

3.125Gbps QUAD SERIAL BACKPLANE TRANSCEIVER

SLLS537A − SEPTEMBER 2002 − REVISED JANUARY 2007

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POST OFFICE BOX 655303

IDDEN function

When held low, the ENABLE pin disables all quiescent power in both the analog and digital circuitry. This allows

loopback testing

The TLK3104SCGNT can provide a self-test function by enabling the internal loop-back path with the assertion

of LPENx for each channel. Enabling this pin causes the serial transmitted data to be routed internally to the

receiver for that channel. The parallel data output can be compared to the parallel input data for that channel

to provide functional verification. The external serial output is held in a high-impedance state during the

loop-back testing.

JTAG

The TLK3104SCGNT has a JTAG test control interface to allow for boundary scan. However, due to the

sensitivity of the high-speed serial pins, TXxP/N and RXxP/N are not scanned under JTAG.

power-on reset

Upon application of minimum valid power, the TLK3104SCGNT generates a power-on reset. During the

power-on reset the receive data pins RDx[0..3] are 3-state and the recovered receive clock pins RCx are held

low. The length of the power-on reset cycle is dependent upon the reference clock (RFCP/RFCN) frequency,

but is less than 1 ms in duration.