TLK3104SCGNT

3.125Gbps QUAD SERIAL BACKPLANE TRANSCEIVER

SLLS537A − SEPTEMBER 2002 − REVISED JANUARY 2007

9

POST OFFICE BOX 655303

detailed description (continued)

D

Deserializer

D

Serializer

TX PLL

TXN

TXP

Repeater Mode

RXN

RXP

Recovered

Clock

Figure 1. Repeater Mode Block Diagram

transmit interface

An external reference clock, RFCP/N is needed for the on-chip PLL and the clock/data recovery loop. A data

FIFO is placed in the transmit data path to resolve any phase difference between the TCx and RFC.

The transmitter portion registers the incoming 4-bit wide data (TDx[0:3]) on the rising edge of the TCx. The

parallel data is then demuxed into an 8-bit wide data bus. After going through the FIFO, which decouples the

clock domain to the RFC, the 8-bit data is encoded into 10-bit data with the K code control bit, TDKx using an

8-b/10-b encoder. The data is then serialized and transmitted sequentially over the differential high-speed I/O

channel. The clock multiplier multiplies the parallel data rate by a factor of five, providing the high-speed clock,

which is fed to the parallel-to-serial shift register. Data is transmitted LSB (D0) first.

parallel transmit data bus

The transmit bus interface accepts 4-bit wide LVDS parallel data at the TD[0:3]x pins. A 100-

Ω on-chip

termination resistor is placed differentially at each LVDS input pair. The rising edge of TCx is used to latch the

data (see Figure 2). Special code words, like comma, could be sent through the control of the TDKx pin. The

internal demultiplexing converts the 4-bit data bus plus the TDK control bit into an 8-bit data bus plus one control

bit. Figure 3 shows the data mapping used by the demux function. The byte boundary is defined by the TDK

signal. When it is asserted, only the first half of the 8-bit word is pulsed, which is used to group the correct 8 bits

into a byte. Table 2 shows the K codes supported by the TLK3104SCGNT.

Each LVDS input pair also supports a fail-safe operation in case that the link is broken or the LVDS driver on

the other end is disabled. Under such circumstances, the LVDS input forces its output to be low until the link

is reconnected or the LVDS driver is reactivated. This prevents noise from being amplified through the LVDS

input circuit while there is no active data on the line.