TLK3104SCGNT

3.125Gbps QUAD SERIAL BACKPLANE TRANSCEIVER

SLLS537A − SEPTEMBER 2002 − REVISED JANUARY 2007

13

POST OFFICE BOX 655303

channel clock to serial transmit clock synchronization (continued)

Channel

Logic

Protocol Device

TX

FIFO

Channel A

TCA

TLK3104SCGNT

Serdes

Core

Data A

Channel

Logic

TX

FIFO

Channel B

TCB

Data B

Serdes

Core

Channel

Logic

TX

FIFO

Channel C

TCC

Data C

Serdes

Core

Channel

Logic

TX

FIFO

Channel D

TCD

Data D

Serdes

Core

Xtal Osc.

RFCP/RFCN

Figure 6. Transmit and Reference Clock Relationship

PRBS generator and verifier

MDIO or by asserting the PRBSEN pin high, the PRBS pattern is generated and fed into the 10-bit

parallel-to-serial converter. Data from the normal input source is ignored during the self-test mode. The PRBS

pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The

output can be sent to a bit error rate tester (BERT), the receiver of another TLK3104SCGNT channel, or can

be looped back to the receive input of the particular channel. Since the PRBS is not really random but a

predetermined sequence of ones and zeroes, the data can be captured and checked for errors by a BERT.

Result reporting of the self-test is available on the RDKx pins and MDIO registers when this test mode is

enabled. Through a mux controlled by PRBSEN, one bit test result (pass or fail) is sent to the RDKx pin. A high

state on these pins under this test mode indicates an error free link. MDIO register 22.4 to 22.7 are also for the

PRBS test indicating the status of the test and they can be accessed through the MDIO interface.

When the PRBS testing is enabled through the PRBSEN pin or MDIO, the SYNCEN pin is used for production

testing only. The user needs to make sure this pin is grounded for proper PRBS testing.