SST89C54 datasheet(21/50 Pages) SST

21 / 50 page

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FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

The BYTE-PROGRAM and BURST-PROGRAM com-

mands are used for programming new data into the

memory array. Selection of which Program command to

use will be dependent upon the desired programming

field size. Programming will not take place if any security

locks are enabled on the selected memory block.

The BYTE-PROGRAM command programs data into a

single byte. Ports P0[7:0] are used for data in. The

memory location is selected by P1[7:0], P2[5:0], and

P3[5:4] (A15-A0). The BYTE-PROGRAM command is

selected by the binary code of 11b on P3[7:6] and 10b on

P2[7:6]. See Figure 14 for timing waveforms.

The BURST-PROGRAM command programs data to an

entire row, sequentially byte-by-byte. Ports P0[7:0] are

used for data in. The memory location is selected

by P1[7:0], P2[5:0], and P3[5:4] (A15-A0). The BURST-

PROGRAM command is selected by the binary code of

01b on P3[7:6] and 10b on P2[7:6]. See Figure 15 for

timing waveforms.

The BYTE-VERIFY command allows the user to verify

that the SST89C54/58 correctly performed an Erase or

Program command. Ports P0[7:0] are used for data out.

The memory location is selected by P1[7:0], P2[5:0], and

P3[5:4] (A15-A0). The BYTE-VERIFY command is se-

lected by the binary code of 11b on P3[7:6] and 00b on

P2[7:6]. This command will be disabled if any security

locks are enabled on the selected memory block. See

Figure 16 for timing waveforms.

The PROG-SB1, PROG-SB2, PROG-SB3 commands

program the security bits, the functions of these bits are

described in a Security Lock section and also in Table 8.

Once programmed, these bits can only be cleared

through a CHIP-ERASE command.

The PROG-RB1, and PROG-RB0 commands program

the Re-Map[1:0] bits. The Re-Map[1:0] bits determine

the Memory Re-mapping default option on reset. Upon

completion of the Reset sequence, the MAP_EN[1:0]

bits are initialized to the default value set by the Re-

Map[1:0] bits according to Table 2. Subsequent program

manipulation of MAP_EN[1:0] bits will alter the Memory

Re-mapping option but will not change the Re-Map[1:0]

bits. Therefore, any changes to MAP_EN[1:0], without

corresponding updates to Re-Map[1:0], will not survive a

Reset cycle.

If an External Host Mode command, except for CHIP-

ERASE, is issued to a locked memory block, the device

will ignore this command.

External Host Mode Clock Source

In External Host Mode, an internal oscillator will provide

clocking for the SST89C54/58. The on-chip oscillator will

be turned on as the SST89C54/58 enters External Host

Mode; i.e. when PSEN# goes low while RST is high. The

oscillator provides both clocking for the Flash Control

Unit as well as timing references for Program and Erase

operations. During External Host Mode, the CPU core is

held in reset. Upon exit from External Host Mode, the

internal oscillator is turned off.

The same oscillator also provides the time base for the

watchdog timer and timing references for IAP Mode

Program and Erase operations. See more detailed de-

scription in later sections.

Arming Command

An arming command sequence must take place before

any External Host Mode sequence command is recog-

nized by the SST89C54/58. This prevents accidental

triggering of External Host Mode Commands due to

noise or programmer error. The arming command is as

follows:

PSEN# goes low while RST is high. This will get

the machine in External Host Mode, re-configur-

ing the pins.

A Read-ID command is issued and held for 1 ms.

After the above sequence, all other External Host Mode

commands are enabled. Before the Read-ID command

is received, all other External Host commands received

are ignored.

Programming a SST89C54/58

To program data into the memory array, apply power

supply voltage (VDD) to VDD and RST pins, and perform

the following steps:

Maintain RST high and toggle PSEN# from logic

high to low, in sequence per the appropriate timing

diagram.

Raise EA# High (either VIH or VH).

Issue READ-ID command to enable the External

Host Mode.

Verify that the memory blocks or sectors for pro-

gramming is in the erased state, FFh. If they are not

erased, then erase them using the appropriate

Erase command.

Select the memory location using the address lines

(P1[7:0], P2[5:0], P3[5:4]).

Present the data in on P0[7:0].

Pulse ALE/PROG#, observing minimum pulse

width.

Wait for low to high transition on READY/BUSY#

(P3[3]).

Repeat steps 5 – 8 until programming is finished.

10. Verify the flash memory contents.

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