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SST89C54 Datasheet(PDF) 35 Page - Silicon Storage Technology, Inc |
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SST89C54 Datasheet(HTML) 35 Page - Silicon Storage Technology, Inc |
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35 / 50 page ![]() 35 © 2000 Silicon Storage Technology, Inc. 344-2 8/00 FlashFlex51 MCU SST89C54 / SST89C58 Preliminary Specifications 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 POWER-SAVING MODES The SST89C54/58 provides three power saving modes of operation for applications where power consumption is critical. The three power saving modes are: Idle, Power Down and Standby (Stop Clock). Idle Idle mode is entered by a software command which sets the IDL bit in the PCON register. In Idle mode the program counter (PC) is stopped. The system clock continues to run and all interrupts and peripheral func- tions (timers/counters, serial port, etc.) are active. In this mode the power dissipation is approximately 25% of the fully active device. The SST89C54/58 exits Idle mode through either a system interrupt or a hardware reset. The interrupt clears the IDL bit and the program resumes execution begin- ning at the instruction immediately following the one which invoked the Idle mode. A hardware reset starts the device similar to power-on reset. FIGURE 20: POWER-ON RESET CIRCUIT Power Down The Power Down mode is also entered by a software command which sets the PD bit in the PCON register. In Power Down mode, the clock is stopped and external interrupts are active for level sensitive interrupt only. Power Down mode reduces the current dissipation to 15µA, typical. The SST89C54/58 exits Power Down mode through either an enabled external level sensitive interrupt or a hardware reset. The interrupt clears the PD bit and the program resumes execution beginning at the instruction immediately following the one which invoked the Power Down mode. A hardware reset starts the device similar to power-on reset. Standby (Stop Clock) Standby mode is similar to Power Down mode, except that Power Down mode is initiated by a software com- mand and Standby mode is initiated by external hard- ware gating off the external clock to the SST89C54/58 device. The current dissipation is reduced to 15µA, typical. The on-chip SRAM and SFR data are maintained in Standby mode. The device resumes operation at the next instruction when the clock is reapplied to the part. Table 10 outlines the different power-saving modes, including entry and exit procedures and MCU functionality. 344 ILL F31.1 VDD VDD 10µF + - 8.2K SST89C54/58 RST XTAL2 XTAL1 12MHz C1 C2 |
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