SST89C54 datasheet(7/50 Pages) SST

7 / 50 page

344-2 8/00

FlashFlex51 MCU

SST89C54 / SST89C58

Preliminary Specifications

PIN DESCRIPTIONS (CONTINUED)

Symbol

Type1

Name and Functions

PSEN#

O/I

Program Store Enable: PSEN# is the Read strobe to External Program

Memory. When the SST89C54/58 are executing from Internal Program

Memory, PSEN# is inactive (high). When the device is executing code from

External Program Memory, PSEN# is activated twice each machine cycle,

except that two PSEN# activations are skipped during each access to External

Data Memory. While the RST input is continually held high (for more than ten

machine cycles), a forced high-to-low input transition on the PSEN# pin will bring

the device into the “External Host” mode for the internal flash memory

programming operation.

RST

Reset: A high logic state on this pin for two machine cycles (at least 24 oscillator

periods), while the oscillator is running resets the device. After a successful reset

is completed, if the PSEN# pin is driven by an input force with a high-to-low

transition while the RST input pin is continually held high, the device will enter the

“External Host” mode for the internal flash memory programming operation,

otherwise the device will enter the “Normal” operation mode.

EA#

External Access Enable: EA# must be connected to VSS in order to enable the

SST89C54/58 to fetch code from External Program Memory locations starting

at 0000h up to FFFFh. Note, however, that if the Security Lock is activated on

either block, the logic level at EA# is internally latched during reset. EA# must be

connected to VDD for internal program execution. The EA# pin can tolerate a high

voltage2 of 12V (see Electrical Specification).

ALE/PROG#

I/O

Address Latch Enable: ALE is the output signal for latching the low byte of the

address during accesses to external memory. This pin is also the programming

pulse input (PROG#).

XTAL1

Oscillator: Input and output to the inverting oscillator amplifier. XTAL1 is input to

XTAL2

internal clock generation circuits from an external clock source.

VDD

Power Supply: Supply voltage during normal, Idle, Power Down, and Standby

Mode operations.

Vss

Ground: Circuit ground. (0V reference)

344 PGM T1.6

Note: 1 )

I = Input

O = Output

It is not necessary to receive a 12V programming supply voltage during flash programming.

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