TPS65921 datasheet(39/58 Pages) TI1

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TPS65921

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SWCS048F – MARCH 2010 – REVISED MARCH 2012

The short-circuit current for the LDOs and DCDCs in the TPS65921 device is approximately twice the maximum

load current. In certain cases when the output of the block is shorted to ground, the power dissipation can

exceed the 1.2 W requirement if no action is taken. A short-circuit protection scheme is included in the

TPS65921 device to ensure that if the output of an LDO or DCDC is short-circuited, then the power dissipation

does not exceed the 1.2 W level.

The three USB LDOs VUSB3V1, VUSB1V8, and VUSB1V5 are included in this short circuit protection scheme

which monitors the LDO output voltage at a frequency of 1 Hz, and generates an interrupt when a short circuit is

detected.

The scheme compares the LDO output voltage to a reference voltage and detects a short circuit if the LDO

voltage drops below this reference value (0.5 V or 0.75 V programmable). In the case of the VUSB3V1 and

VUSB1V8 LDOs, the reference is compared with a divided down voltage (1.5 V typical).

If a short circuit is detected on VUSB3V1, then the power subchip FSM switches this LDO to sleep-mode.

If a short circuit is detected on VUSB1V8 or VUSB1V5, then the power subchip FSM switches the relevant LDO

off.

Power Reference

The bandgap voltage reference is filtered (RC filter), using an external capacitor connected across the VREF

output and an analog ground (REFGND). The VREF voltage is scaled, distributed, and buffered inside the

device. The bandgap is started in fast mode (not filtered) and is set automatically by the power state-machine in

slow mode (filtered, less noisy) after switch on.

Power Use Cases

The TPS65921 device has two modes:

•

Master: The TPS65921 device decides to power up or down the system and control the other power ICs in

the system with the SYSEN output.

•

Slave: The TPS65921 device is controlled by another power IC with a digital signal on the PWRON input.

There is no battery management in slave mode.

The modes corresponding to BOOT0–BOOT1 combination value are:

NAME

DESCRIPTION

BOOT0

BOOT1

MC021(1)

Master_C021_Generic 10

SC021

Slave_C021_Generic 11

(1)

Boot mode for OMAP3430 is c021 Master boot mode.

Process modes define:

•

The boot voltage for the host core

•

The boot sequence associated with the process

•

The DVFS protocol associated with the process

MODE

C021.M

Boot core voltage

1.2 V

Power sequence

VIO followed by VPLL1, VDD2, VDD1

DVFS protocol

SmartReflex interface (I2C high speed)

Regulator states depending on use cases:

REGULATOR

MODE: C021 (MASTER/SLAVE)

BACKUP

WAIT ON

SLEEP NO LOAD

ACTIVE NO LOAD

VAUX2

OFF

VMMC1

OFF

VPLL1

OFF

SLEEP

VDAC

OFF

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TPS65921 Datasheet(PDF) 39 Page - Texas Instruments

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