TUSB8020A, TUSB8040A

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SLLSEA7B – MAY 2012 – REVISED AUGUST 2012

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POWER UP AND RESET

The TUSB80x0A does not have specific power sequencing requirements with respect to the core power

(VDD11) or I/O and analog power (VDD33). The core power (VDD11) or I/O power (VDD33) may be

powered up for an indefinite period of time while the other is not powered up if all of these constraints are

met:

•

All maximum ratings and recommended operating conditions are observed.

•

All warnings about exposure to maximum rated and recommended conditions are observed,

particularly junction temperature. These apply to power transitions as well as normal operation.

•

Bus contention while VDD33 is powered up must be limited to 100 hours over the projected life-time of

the device.

•

Bus contention while VDD33 is powered down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered

down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in

the recommended operating range to the de-assertion of GRSTz. This can be generated using

programmable-delay supervisory device or using an RC circuit.

A supply bus is powered up when the voltage is within the recommended operating range. It is powered

down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required. This is defined as the time when the power supplies are in

the recommended operating range to the de-assertion of GRSTz. This can be generated using

programmable-delay supervisory device or using an RC circuit.

Copyright © 2012, Texas Instruments Incorporated

POWER UP AND RESET

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Product Folder Links: TUSB8020A TUSB8040A