L99PM62XP datasheet(26/98 Pages) STMICROELECTRONICS

26 / 98 page

Description

L99PM62XP

26/98

Doc ID 16363 Rev 3

The fail safe functionality is also available in V1 standby mode. During V1 standby mode the

fails safe mode is entered in the following cases:

●

V1 undervoltage (V1 < Vrth for t > 8 µs)

●

Watchdog failure (if watchdog still running due to IV1 > Icmp)

●

Thermal shutdown TSD2

In fail safe mode the L99PM62 returns to a default. The fail safe condition is indicated to the

remaining system in the global status register. The conditions during fails safe mode are:

●

All outputs are turned off

●

All control registers are set to default values (except OUT3/FSO configuration)

●

Write operations to control registers are blocked until the fail safe condition is cleared

(see

Table 5)

●

LIN and HS CAN transmitter, OpAmps and SPI remain on

●

Corresponding failure bits in status registers are set.

●

FSO Bit (Bit 0 global status register) is set

●

OUT3/FSO is activated if configured as fail safe output

If OUT3 is configured as FSO, the internal fail safe mode can be monitored at OUT3 (high-

side driver is turned on in fail-safe mode). Self protection features for OUT3 when configured

as FSO are active (see

Section 3.3: High-side driver outputs ).

OUT3 is configured as fail safe output by default. It can be configured to normal high-side

driver operation by SPI. It this case, the configuration remains until Vs power on.

If the fail safe mode was entered it keeps active until the fail safe condition is removed and

the fail safe was read by spi. depending on the root cause of the fail safe operation, the

actions to exit fail safe mode are as shown in the following table.

If the fail-safe condition persists and all attempts to return to normal system operation fail,

the L99PM62 enters the

forced VBAT standby mode in order to prevent damage to the

Table 5.

Fail safe conditions and exit modes

Failure source

Failure condition

Diagnosis

Exit from fail-safe mode

µC (oscillator)

Watchdog early write

failure or expired window

Fail-safe = 1

WDfail = n+1

TRIG = 1 during LOWi and

read fail-safe bit

Short at turn-on

Fail-safe = 1

Forced Sleep TSD2/SHTV1 = 1

Read&Clear SR3 after wake

Undervoltage

Fail-safe = 1

V1fail = 1

(1)

V1 > Vrth

Read Fail-safe bit

Temperature

Tj > TSD2

Fail-safe = 1

TW = 1

TSD1 = 1

TSD2 = 1

Tj < TSD2

Read&Clear SR3

SPI

DI short to GND or VCC

Fail-safe = 1

Valid SPI command

if V1 < V1fail (for t >2µs)

The fail-safe bit is located in the global status register (Bit 0)

multiple failures – entering forced VBAT standby mode

L99PM62XP Datasheet(PDF) 26 Page - STMicroelectronics

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