PXD10 datasheet(23/130 Pages) FREESCALE

23 / 130 page

Overview

PXD10 Microcontroller Data Sheet, Rev. 1

Freescale Semiconductor

•

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

•

Ability to modify the ISR or task priority.

— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing

shared resources.

•

External non-maskable interrupt directly accessing the main core critical interrupt mechanism

•

32 external interrupts

1.6.24

System Integration Unit (SIU)

The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O

(GPIO), internal peripheral multiplexing, and the system reset operation.

The GPIO features the following:

•

As many as four levels of internal pin multiplexing, allowing exceptional flexibility in the

allocation of device functions for each package

•

Centralized general purpose input output (GPIO) control of as many as 132 input/output pins

(package dependent)

•

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

•

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

•

All peripheral pins can be alternatively configured as both general purpose input or output pins

except ADC channels which support alternative configuration as general purpose inputs

•

Direct readback of the pin value supported on all digital output pins through the SIU

•

Configurable digital input filter that can be applied to as many as 14 general purpose input pins for

noise elimination on external interrupts

•

prevent modification until next reset.

1.6.25

System Clocks and Clock Generation Modules

The system clock on the PXD10 can be derived from an external oscillator, an on-chip FMPLL, or the

internal 16 MHz oscillator.

•

The source system clock frequency can be changed via an on-chip programmable clock divider (

1

2).

•

Additional programmable peripheral bus clock divider ratio (

1 to 16)

•

The PXD10 has two on-chip FMPLLs—the primary module and an auxiliary module.

— Each features the following:

– Input clock frequency from 4 MHz to 16 MHz

– Lock detect circuitry continuously monitors lock status

– Loss Of Clock (LOC) detection for reference and feedback clocks

– On-chip loop filter (for improved electromagnetic interference performance and reduction

of number of external components required)

PXD10 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc

PXD10 Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc

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