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LCX038ART

3. 12-dot Simultaneous Sampling

The horizontal shift register samples signals VSIG1 to VSIG12 simultaneously. This requires phase

matching between signals VSIG1 to VSIG12 to prevent the horizontal resolution from deteriorating. Thus,

phase matching between each signal is required using an external signal delaying circuit before applying

the video signal to the LCD panel.

The block diagram of the delaying procedure using the sample-and-hold method is as follows. The following

phase relationship diagram indicates the phase setting for right scan (RGT = High level). For left scan (RGT =

Low level), the phase settings for signals VSIG1 to VSIG12 are exactly reversed.

VSIG1

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

S/H

CK12

VSIG2

VSIG3

VSIG4

VSIG5

VSIG6

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12

3

4

5

6

7

8

9

10

11

12

13

14

S/H

CK11

S/H

CK10

S/H

CK9

S/H

CK8

S/H

CK7

S/H

CK6

S/H

CK5

S/H

CK4

S/H

CK3

S/H

CK2

S/H

CK1

VSIG1

VSIG2

VSIG3

VSIG4

VSIG5

VSIG6

VSIG7

VSIG8

VSIG9

VSIG10

VSIG11

VSIG12