AD1859 datasheet(13/16 Pages) AD

13 / 16 page

AD1859

REV. A

–13–

PCB and Ground Plane Recommendations

The AD1859 ideally should be located above a split ground

plane, with the digital pins over the digital ground plane, and

the analog pins over the analog ground plane. The split should

occur between Pins 6 and 7 and between Pins 22 and 23 as

shown in Figure 19. The ground planes should be tied together

at one spot underneath the center of the package with an ap-

proximately 3 mm trace. This ground plane strategy minimizes

RF transmission and reception as well as maximizes the AD1859’s

analog audio performance.

CMOUT

DEEMP

EMPL

OUTL

AGND

MUTE

18/16

IDPM0

IDPM1

SDATA

LRCLK

BCLK

PD/RST

ANALOG

GROUND PLANE

DIGITAL

GROUND PLANE

FILT

FGND

AVDD

EMPR

OUTR

CLATCH

CDATA

CCLK

DGND

DVDD

XTALI/MCLK

XTALO

Figure 19. Recommended Ground Plane

TIMING DIAGRAMS

The serial data port timing is shown in Figures 20 and 21. The

minimum bit clock HI pulse width is tDBH, and the minimum bit

clock LO pulse width is tDBL. The minimum bit clock period is

tDBP. The left/right clock minimum setup time is tDLS, and the

left/right clock minimum hold time is tDLH. The serial data mini-

mum setup time is tDDS, and the minimum serial data hold time

is tDDH.

BCLK

SDATA

LEFT-

JUSTIFIED

MODE

SDATA

RIGHT-

JUSTIFIED

MODE

SDATA

I2S-

JUSTIFIED

MODE

MSB

LSB

tDBH

tDBP

tDBL

tDLS

tDDS

tDDH

tDDS

tDDH

tDDS

tDDH

tDDS

tDDH

MSB

MSB-1

RCLK

Figure 20. Serial Data Port Timing

tDBH

tDBL

tDLS

tDDH

tDDS

BCLK

SDATA

LEFT-JUSTIFIED

DSP SERIAL

PORT STYLE

MODE

MSB

MSB-1

tDBP

tDLH

LRCLK

Figure 21. Serial Data Input Port Timing DSP Serial

Port Style

The serial control port timing is shown in Figure 22. The mini-

mum control clock HI pulse width is tCCH, and the minimum

control clock LO pulse width is tCCL. The minimum control

clock period is tCCP. The control data minimum setup time is

tCSU, and the minimum control data hold time is tCHD. The

minimum control latch delay is tCLD, the minimum control latch

LO pulse width is tCLL, and the minimum control latch HI pulse

width is tCLH.

CCLK

tCCL

tCCP

tCCH

CDATA

tCSU

tCHD

CLATCH

tCLD

tCLH

tCLL

LSB

Figure 22. Serial Control Port Timing

The master clock (or crystal input) and power down/reset tim-

ing is shown in Figure 23. The minimum MCLK period is tMCP,

which determines the maximum MCLK frequency at FMC. The

minimum MCLK HI and LO pulse widths are tMCH and tMCL,

respectively. The minimum reset LO pulse width is tPDRP (four

XTALI/MCLK periods) to accomplish a successful AD1859 re-

set operation.

PD/RST

XTALI/MCLK

tPDRP

tMCH

tMCP

tMCL

Figure 23. MCLK and Power Down/Reset Timing

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