REV. 0

–7–

CURRENT OUTPUT MODE

One or both channels of the AD1865 can be operated in current

current-to-voltage (I-V) converter. The internal feedback resis-

temperature.

Of course, the AD1865 can also be used in voltage output mode

in order to utilize the onboard I-V converter.

VOLTAGE OUTPUT MODES

As shown on the block diagram, each channel of the AD1865 is

complete with an I-V converter and a feedback resistor. These

can be connected externally to provide direct voltage output

from one or both AD1865 channels. Figure 6 shows these con-

results in the lowest possible component count and achieves the

specifications shown on the Specifications page while operating

at 16

× F

L

S

B

L

S

B

M

S

B

M

S

B

CLK

DL

DR

LL

LR

Figure 8. AD1865 Control Signals

INPUT DATA

Data is transmitted to the AD1865 in a bit stream composed of

18-bit words with a serial, twos complement, MSB first format.

Data Left (DL) and Data Right (DR) are the serial inputs for

the left and right DACs, respectively. Similarly, Latch Left (LL)

and Latch Right (LR) update the left and right DACs. The fall-

ing edge of LL and LR cause the last 18 bits which were clocked

into the Serial Registers to be shifted into the DACs, thereby

updating the DAC outputs. Left and Right channels share the

Clock (CLK) signal. Data is clocked into the input registers on

the rising edge of CLK.

Figure 8 illustrates the general signal requirements for data

transfer for the AD1865.

TIMING

Figure 9 illustrates the specific timing requirements that must

be met in order for the data transfer to be accomplished prop-

erly. The input pins of the AD1865 are both TTL and 5 V

CMOS compatible.

The minimum clock rate of the AD1865 is at least 13.5 MHz.

This clock rate allows data transfer rates of 2

×, 4×, 8× and

16

× F

CLK

DL/DR

LL/LR

>74.1ns

>30ns

>30ns

>40ns

>15ns

>40ns

>40ns

>30ns

>15ns

>15ns

MSB

1st BIT

2nd BIT

LSB

18th BIT

NEXT

WORD

BITS CLOCKED

TO SHIFT REGISTER

INTERNAL DAC INPUT REGISTER

UPDATED WITH 18 MOST RECENT BITS

Figure 9. AD1865 Timing Diagram

Digital Circuit Considerations–AD1865