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AD1892 Datasheet(PDF) 22 Page - Analog Devices |
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AD1892 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 24 page  AD1892 –22– REV. 0 TIMING DIAGRAMS tPDRP MCLK PD/RST tRS tMCP Figure 35. MCLK and Power-Down/Reset Timing BCLK OUTPUT L RCLK OUTPUT SDATA OUTPUT LEFT-JUSTIFIED MODE SDATA OUTPUT 12S-JUSTIFIED MODE SDATA OUTPUT RIGHT-JUSTIFIED MODE MCLK INPUT (NOT TO SCALE) MSB MSB-1 MSB MSB LSB tDDS tDDP tDDH tDDS tDDP tDDH tDDS tDDH tDDS tDDP tDDH tLDM tBDM Figure 36. Serial Data Output Port Timing CS CCLK SDI SDO tCCP tCCH tCCL tCSU tCHD MSB LSB LSB+1 LSB tCLH tCLK tCOH Figure 37. Serial Control Port Timing |
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