Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 15 -

Confidential Information

The VDDRTC was designed to interface with either a:

•

Lithium Battery or

•

Capacitor in the range of 0.4F (maximum for ~24 hours

standby) to 8mF (~30 minutes standby)

Reset

The AD6426 is reset by setting the RESET pin to GND. This

will reset the H8-processor, the Channel Codec, the internal

DSP as well as the LCD controller interface and Boot ROM

logic. Both the DSP and the Channel Codec will be held in

reset until the RESET register is written to by the H8. At least

50 CLKIN cycles must elapse before deasserting the RESET

pin and at least a further 100 cycles before writing to the

RESET register.

For reset at power up, the DSP must be held in reset for at

least 2000 clock cycles to enable the internal PLL to lock.

The RESET CC Control Register 35 contains the following

flags:

Bit

Function

3

EVBC Reset

2

DSP Reset

0

Channel Codec Reset

Additionally 8 functional modules can be reset under control

of the two SWRESET registers:

Bit

SWRESET 1 CC Control Register 46

3

Encryption Software Reset

2

EVBC Interface Software Reset

1

DSP Interface Software Reset

0

Synthesizer Interface Software Reset

Bit

SWRESET 2 CC Control Register 47

3

Decode Software Reset

2

Deinterleave Software Reset

1

Interleave Software Reset

0

Encode Software Reset

The JTAG circuitry is reset by a power-on reset mechanism.

Further resets must be done by asserting the TMS input high

for at least five TCK clock cycles. When JTAG compliance is

re-enabled, the JTAG is reset forcing the AD6426 into its

normal mode of operation, selecting the BYPASS register by

default.

The H8 fetches its program start vector from location 0x0000

in segment zero. This can either be from external ROM or

internal Boot ROM, depending on the status of the

BOOTCODE pin.

Interrupts

The interrupts are controlled by the two CC Control Registers

77 and 78. These registers only apply to Emulation Mode, in

that they define which of the interrupts are able to assert

CCIRQ2.

Bit

IRQ ENABLE CC Control Register 77

5

IRQ 5 Enable

4

IRQ 4 Enable

3

IRQ 3 Enable

2

IRQ 2 Enable

Bit

IRQ LATCH CC Control Register 78

5

IRQ 5 active

4

IRQ 4 active

3

IRQ 3 active

2

IRQ 2 active

NMI

The non-maskable interrupt NMI input of the H8 processor is

multiplexed with the IRQ6 pin. IRQ6 is the default function,

though asserting the NMI Select flag in CC Control Register 7

will select the NMI function. When not selected, NMI will be

tied off high internally, though it remains driven by the JTAG

port for test purposes. The signal is programmable to be edge

or level sensitive. It defaults to falling edge. The edge polarity

can be changed by programming the H8. However, if

FLASHPWD is used then the same setting must be applied to

CC Control Register 77. The default of zero implies falling

edge sensitive. This way NMI going active can correctly de-

assert FLASHPWD. The NMI can be used for test purposes or

user defined features. NMI is capable of bringing the control

processor out of software standby mode and therefore suitable

for functions such as alarm inputs, power management etc.

During manufacture the NMI can be used to trigger special

test code.

In addition NMI can be generated internally thus freeing up

the IRQ6 PIN. In this mode the TXENABLE NMI will occur

on the rising edge of the TXENABLE as seen at the pin. The

H8 should be set up for a negative edge NMI in this case.

Setting bit 5 in the SERDISPLAY/NMI H8 Peripheral Control

Register 106 to a ONE enables the TXENABLE NMI.

However, the Layer 1 Software must program the external INT

pin to INT6 before the register bit is set.