Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 30 -

Confidential Information

Pin Name in

Normal Mode (A)

Pin Function in

Emulation Mode (D)

GPO10

WAIT

O

GPCS

-

TRI

FLASHPWD

Forced High

O

DISPLAYCS

DISPLAYCS

I/O

GPIO0

Reserved

O

GPIO1

Forced High/

BANDSELECT1

O

GPIO2

Forced High/

BANDSELECT0

O

GPIO3

Forced High/DISPA0

O

GPIO4

Forced High/DISPCLK

O

GPIO5

Forced High/BATID

O

GPIO6

Reserved

O

GPIO7

Reserved

TRI

FLASHPWD can also be used as WAIT input, in which case it

is routed through and gated with the LCDWAIT to be output

on the WAIT output pin GPO10/ADD20. If the on-chip LCD

controller is not used in emulation, then ADD20 pin can be

used as ccGPO(10).

FEATURE MODES

Two additional features can be enabled under software

control.

These are; DAI Mode (Digital Audio Interface) and HSL

Mode (High Speed Logging) used to monitor the operation of

the on-chip DSP.

DAI Mode

This mode is selected during type approval, when Digital

Audio Interface is required. To enable this feature, the

JTAGEN pin must be de-asserted, upon which the JTAG pins

TMS, TDI and TDO are re-assigned as shown in Table 25.

The default feature mode thus enabled is DAI. In addition, the

voiceband serial port signals are made available through the

USC to facilitate testing of the speech transcoder as well as

the phone’s acoustic properties. The DAI box interface product

is available upon request from Analog Devices.

Table 25. DAI Mode

AD6426 Pin

Function in DAI Mode

I/O

VSCLK

MSCLK

I

VSFS

MSFS

I

VSDO

MSRXD

O

VSDI

MSTXD

I

TMS

DAIRESET

O

TDI

DAI1

O

TDO

DAI0

I

High Speed Logging

This mode is selected for monitoring the operation of the

internal DSP during the development and field test phase.

When the JTAGEN pin is de-asserted and the HSLEnable flag

in the TESTADDRESS CC Control Register 33 is set, a high

speed logging port is mapped on the JTAG- and EEPROM

pins as shown in Table 26. The internal DSP must then be

instructed via Layer 1 to output logging messages onto the

HSL pins.

Table 26. HSL Mode

AD6426 Pin

Function in HSL Mode

TCK

HSLDO0

O

TMS

HSLDO1

O

TDO

HSLDO2

O

TDI

HSLDO3

O

EEPROMCLK

HSLCLK

O

EERPROMEN

HSLFS

O

The High Speed Logging port (HSL) is an unidirectional port

which supplies nibble-wide synchronous data from the internal

DSP to an external data logger. The data logger will be

connected to a PC which will be responsible for presenting the

data to the user. The PC is able to configure the HSL via

either one of the serial interfaces.

The HSL is enabled as follows:

•

The JTAGEN pin is set to 0

•

The H8 enables the HSL logic by setting the HSLEnable

flag

•

On a command issued through the Data Interface, the H8

configures the DSP software to enable HSL

The HSLEnable flag is used to deselect DAIRESET in favor of

the HSL onto the JTAG pins, and enable the HSL onto

EEPROMCLK and EEPROMEN.

The DSP sends data over the port by writing to address 0x000

in the Data Memory map. The writes are full 16-bit writes,

and can occur at a maximum rate of one write per five 39 MHz

clock cycles. Five cycles allow time for the HSL circuit to

serialize the 16 bits of data onto the 4-bit data bus with one

cycle to spare. HSLFS is used to frame the valid data nibbles.

Note that HSCLK is free-running , and that HSLFS and

HSLDO3-0 are synchronized to the rising edge of HSCLK.