Preliminary Technical Information

AD6426

This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no

obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any

infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of Analog Devices.

Revision Preliminary 2.3 (June 9, ´98)

- 35 -

Confidential Information

TIMING CHARACTERISTICS

Radio Interface

Parameter

Comment ( see Figure 16 )

Min

Max

Units

Synthesizer clock period

152

615

ns

Synthesizer clock high

76

307

ns

Synthesizer data setup

60

85

ns

Synthesizer data hold

60

85

ns

Synthesizer enable delay for Type 0

60

85

ns

Synthesizer enable delay for Type 1

-15

10

ns

Synthesizer enable width for Type 1

50

90

ns

SYNTHCLK

SYNTHDATA

SYNTHEN[0:1]

TYPE 0

0

1

2

n-2

n-1

n

t

40

t

41

t

42a

t

43a

t

42b

SYNTHCLK

SYNTHDATA

SYNTHEN[0:1]

TYPE 1

0

1

2

n-2

n-1

n

t

44

t

43b

t

42b

t

42a

t

40

t

41

Figure 16. Synthesizer Interface Timing