PCA6408APW datasheet(6/40 Pages) NXP

Part #	PCA6408APW

Description	Low-voltage, 8-bit I2C-bus and SMBus I/O expander with interrupt output, reset, and configuration registers

PDF	40 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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6 / 40 page

PCA6408A

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Product data sheet

Rev. 1 — 27 September 2012

6 of 40

NXP Semiconductors

PCA6408A

Low-voltage, 8-bit I2C-bus and SMBus I/O expander

Voltage translation

Table 4 shows how to set up VDD levels for the necessary voltage translation between the

I2C-bus and the PCA6408A.

Functional description

Refer to Figure 1 “Block diagram (positive logic)”.

7.1 Device address

The address of the PCA6408A is shown in Figure 5.

ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW

(logic 0) to assign one of the two possible slave addresses. The last bit of the slave

address defines the operation (read or write) to be performed. A HIGH (logic 1) selects a

read operation, while a LOW (logic 0) selects a write operation.

Table 4.

Voltage translation

VDD(I2C-bus) (SDA and SCL of I2C master)

VDD(P) (Port P)

1.8 V

2.5 V

1.8 V

3.3 V

1.8V

2.5 V

1.8 V

2.5 V

3.3 V

2.5V

3.3 V

1.8 V

3.3 V

2.5 V

3.3 V

3.3V

1.8V

2.5V

3.3V

Fig 5.

PCA6408A address

R/W

002aaf539

fixed

slave address

programmable

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