PCA6408APW datasheet(9/40 Pages) NXP

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PCA6408A

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Product data sheet

Rev. 1 — 27 September 2012

9 of 40

NXP Semiconductors

PCA6408A

Low-voltage, 8-bit I2C-bus and SMBus I/O expander

7.5 I/O port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a

high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the

Output port register. In this case, there are low-impedance paths between the I/O pin and

either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the

recommended levels for proper operation.

On power-up or reset, all registers return to default values.

Fig 7.

Simplified schematic of P0 to P7

VDD(P)

P0 to P7

output port

configuration

data from

shift register

write

configuration

pulse

output port

write pulse

polarity

inversion

data from

shift register

write polarity

pulse

input port

read pulse

input port

polarity

inversion

002aaf824

data from

shift register

VSS

to INT

ESD

protection

diode

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