AD7723

–6–

REV. 0

D2

D1

D0

D15

D14

D13

D12

D11

D5

D4

D3

D2

D1

D0

D15

D14

16 CLKIN CYCLES

CLKIN

FSI

SCO

(CFMT = 0)

FSO

SDO

Figure 5. Serial Mode 3. Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output and Serial Data Output

(Refer to Table I for Control Inputs, TSI = DOE)

Table I. Serial Interface (Mode1 = 0, Mode2 = 0)

Decimation

Digital Filter

SCO Frequency

Output Data

Control Inputs

Serial Mode

Ratio (SLDR)

Mode (SLP)

(SCR)

Rate

SLDR SLP

SCR

1

32

Low Pass

1

1

0

1

32

Band Pass

1

0

0

2

32

Low Pass

1

1

1

2

32

Band Pass

1

0

1

3

16

Low Pass

0

1

0

Table II. Parallel Interface

Digital Filter Decimation

Output

Control Inputs

Mode

Ratio

Data Rate

MODE1 MODE2

Band Pass

32

0

1

Low Pass

32

1

0

Low Pass

16

1

1

DOE

SDO

Figure 6. Serial Mode Timing for Data Output Enable and Serial Data Output