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AD7723 Datasheet(PDF) 4 Page - Analog Devices

Part # AD7723
Description  16-Bit, 1.2 MSPS CMOS, Sigma-Delta ADC
PDF  23 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD7723 Datasheet(HTML) 4 Page - Analog Devices

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AD7723
–4–
REV. 0
(AVDD = DVDD = +5 V
5%; AGND = AGND1 = DGND = 0 V; fCLKIN = 19.2 MHz; CL = 50 pF; SFMT =
Logic Low or High, CFMT = Logic Low or High; TA = TMIN to TMAX unless otherwise noted)
TIMING SPECIFICATIONS
Parameter
Symbol
Min
Typ
Max
Units
CLKIN Frequency
FCLK
1
19.2
MHz
CLKIN Period (tCLK = 1/fCLK)t1
0.052
1
µs
CLKIN Low Pulsewidth
t2
0.45
× t
1
0.55
× t
1
CLKIN High Pulsewidth
t3
0.45
× t
1
0.55
× t
1
CLKIN Rise Time
t4
5ns
CLKIN Fall Time
t5
5ns
FSI Setup Time
t6
05
ns
FSI Hold Time
t7
05
ns
FSI High Time1
t8
1tCLK
CLKIN to SCO Delay
t9
25
40
ns
SCO Period2, SCR = 1
t10
2tCLK
SCO Period2, SCR = 0
t10
1tCLK
SCO Transition to FSO High Delay
t11
05
ns
SCO Transition to FSO Low Delay
t12
05
ns
SCO Transition to SDO Valid Delay
t13
512
ns
SCO Transition from FSI3
t14
60
tCLK + t2
SDO Enable Delay Time
t15
520
ns
SDO Disable Delay Time
t16
520
ns
DRDY High Time2
t17
2tCLK
Conversion Time2 (Refer to Tables I and II)
t18
16/32
tCLK
CLKIN to
DRDY Transition
t19
35
50
ns
CLKIN to DATA Valid
t20
20
35
ns
CS/RD Setup Time to CLKIN
t21
0ns
CS/RD Hold Time to CLKIN
t22
20
ns
Data Access Time
t23
20
35
ns
Bus Relinquish Time
t24
20
35
ns
SYNC Input Pulsewidth
t25
1tCLK
SYNC Low Time before CLKIN Rising
t26
0ns
DRDY High Delay after Rising SYNC
t27
25
35
ns
DRDY Low Delay after SYNC Low
t28
2049
tCLK
NOTES
1FSO pulses are gated by the release of FSI (going low).
2Guaranteed by design.
3Frame Sync is initiated on the falling edge of CLKIN.
Specifications subject to change without notice.
IOL
1.6mA
+1.6V
CL
50pF
TO
OUTPUT
PIN
IOH
200 A
Figure 1. Load Circuit for Timing Specifications



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