AD7723

–11–

REV. 0

SERIAL MODE PIN FUNCTION DESCRIPTIONS

Mnemonic

Pin No.

Description

CFMT/

RD

4

Serial Clock Format Logic Input. The clock format pin selects whether the serial data, SDO, is valid

on the rising or falling edge of the serial clock, SCO. When CFMT is logic low, serial data is valid on

the falling edge of the serial clock, SCO. If CFMT is logic high, SDO is valid on the rising edge of

SCO.

DOE/DB4

43

Data Output Enable Logic Input. The DOE pin controls the three-state output buffer of the SDO

pin. The active state of DOE is determined by the logic level on the TSI pin. When the DOE logic

level equals the level on the TSI pin the serial data output, SDO, is active. Otherwise SDO will be

high impedance. SDO can be three-state after a serial data transmission by connecting DOE to FSO.

In normal operations, TSI and DOE should be tied low.

SFMT/DB5

42

Serial Data Format Logic Input. The logic level on the SFMT pin selects the format of the FSO

signal for Serial Mode 1. A logic low makes the FSO output a pulse, one SCO cycle wide at the

beginning of a serial data transmission. With SFMT set to a logic high, the FSO signal is a frame

pulse that is active low for the duration of the 16-bit transmission. For Serial Modes 2 and 3, SFMT

should be tied high.

FSI/DB6

41

Frame Synchronization Logic Input. The FSI input is used to synchronize the AD7723 serial output

data register to an external source and to allow more than one AD7723, operated from a common

master clock, to simultaneously sample its analog input and update its output register.

SCO/DB7

40

Serial Clock Output.

SDO/DB8

38

Serial Data Output. The serial data is shifted out MSB first, synchronous with the SCO. Serial

Mode 1 data transmissions last 32 SCO cycles. After the LSB is output, trailing zeros are output for

the remaining 16 SCO cycles. Serial Modes 2 and 3 data transmissions last 16 SCO cycles.

FSO/DB9

37

Frame Sync Output. FSO indicates the beginning of a word transmission on the SDO pin. Depend-

ing on the logic level of the SFMT pin, the FSO signal is either a positive pulse approximately one

SCO period wide, or a frame pulse which is active low for the duration of the 16-data bit transmission.

TSI/DB10

36

Time Slot Logic Input. The logic level on TSI sets the active state of the DOE pin. With TSI set

logic high, DOE will enable the SDO output buffer when it is a logic high, and vice versa. TSI is

used when two AD7723s are connected to the same serial data bus. When this function is not

needed, TSI and DOE should be tied low.

SLP/DB11

35

Serial Mode Low Pass/Band Pass Filter Select Input. With SLP set logic high, the low-pass filter

response is selected. A logic low selects band pass.

SLDR/DB12

34

Serial Mode Low/High Output Data Rate Select Input. With SLDR set logic high, the low data rate

is selected. A logic low selects the high data rate. The high data rate corresponds to data at the out-

put of the fourth decimation filter (Decimate by 16). The low data rate corresponds to data at the

output of the fifth decimation filter (Decimate by 32).

SCR/DB13

33

Serial Clock Rate Select Input. With SCR set logic low, the serial clock output frequency, SCO, is

equal to the CLKIN frequency. A logic high sets it equal to one-half the CLKIN frequency.

30

DGND/DB14

32

Tie to DGND.

DGND/DB15

31

Tie to DGND.

DGND/

DRDY

5

Tie to DGND.

DGND/DB0

3

Tie to DGND.

DGND/DB1

2

Tie to DGND.

DGND/DB2

1

Tie to DGND.

DGND/DB3

44

Tie to DGND.