AD7723

–9–

REV. 0

PIN FUNCTION DESCRIPTIONS

Mnemonic

Pin No.

Description

11

Digital Logic Power Supply Voltage for the Analog Modulator.

AGND1

9, 10

Digital Logic Power Supply Ground for the Analog Modulator.

17, 26

Positive Power Supply Voltage for the Analog Modulator.

AGND

16, 18, 25

Power Supply Ground for the Analog Modulator.

AGND2

22

Power Supply Ground Return to the Reference Circuitry, REF2, of the Analog Modulator.

39

Digital Power Supply Voltage; +5 V

± 5%.

DGND

6, 28

Ground Reference for Digital Circuitry.

REF1

21

Reference Output. REF1 connects through 3 k

Ω to the output of the internal 2.5 V reference and to

a buffer amplifier that drives the

Σ−∆ modulator.

REF2

23

Reference Input. REF2 connects to the output of an internal buffer amplifier that drives the

Σ−∆

modulator. When REF2 is used as an input, REF1 must be connected to AGND to disable the inter-

nal buffer amplifier.

VIN(+)

20

Positive Terminal of the Differential Analog Input.

VIN(–)

19

Negative Terminal of the Differential Analog Input.

UNI

24

Analog Input Range Select Input. The UNI pin selects the analog input range for either bipolar or unipo-

lar operation. A logic high input selects unipolar operation and a logic low selects bipolar operation.

CLKIN

12

Clock Input. An external clock source can be applied directly to this pin with XTAL_OFF tied high.

Alternatively, a parallel resonant fundamental frequency crystal, in parallel with a 1 M

Ω resistor can

be connected between the XTAL pin and the CLKIN pin with XTAL_OFF tied low. External

capacitors are then required from the CLKIN and XTAL pins to ground. Consult the crystal

manufacturer’s recommendation for the load capacitors.

XTAL

13

Input to Crystal Oscillator Amplifier. If an external clock is used, XTAL should be tied to AGND1.

XTAL_OFF

14

Oscillator Enable Input. A logic high disables the crystal oscillator amplifier to allow use of an exter-

nal clock source. Set low when using an external crystal between the CLKIN and XTAL pins.

MODE1/2

8, 7

Mode Control Inputs. The MODE1 and MODE2 pins choose either parallel or serial data interface

operation and select the operating mode for the digital filter in parallel mode. Refer to Tables I and II.

HALF_PWR

15

When set high, the power dissipation is reduced by approximately one-half and a maximum CLKIN

frequency of 10 MHz applies.

SYNC

29

Synchronization Logic Input. When using more than one AD7723, operated from a common master

clock, SYNC allows each ADC to simultaneously sample its analog input and update its output

register. A rising edge resets the AD7723 digital filter sequencer counter to zero. When the rising

edge of CLKIN senses a logic low on SYNC, the reset state is released. Because the digital filter and

sequencer are completely reset during this action, SYNC pulses cannot be applied continuously.

STBY

27

Standby Logic Input. A logic high sets the AD7723 into the power-down state.