AD7723 datasheet(20/23 Pages) AD

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AD7723

–20–

REV. 0

SERIAL INTERFACE

The AD7723’s serial data interface can operate in three modes,

depending on the application requirements. The timing dia-

grams in Figures 3, 4 and 5 show how the AD7723 may be used

to transmit its conversion results. Table I shows the control

inputs required to select each serial mode, and the digital filter

operating mode. The AD7723 operates solely in the master

mode providing three serial data output pins for transfer of the

conversion results. The serial data clock output, SCO, serial

data output, SDO, and frame sync output, FSO, are all synchro-

nous with CLKIN. FSO is continuously output at the conversion

rate of the ADC.

Serial data shifts out of the SDO pin synchronous with SCO.

The FSO is used to frame the output data transmission to an

external device. An output data transmission is either 16 or 32

SCO cycles in duration (refer to Table I). Serial data shifts out

of the SDO pin, MSB first, LSB last, for a duration of 16 SCO

cycles. In Serial Mode 1, SDO outputs zeros for the last 16

SCO cycles of the 32-cycle data transmission frame.

The clock format pin, CFMT, selects the active edge of SCO.

With CFMT tied logic low, the serial interface outputs FSO and

SDO change state on the SCO rising edge and are valid on the

falling edge of SCO. With CFMT set high, FSO and SDO

change state on the falling SCO edge and are valid on the SCO

rising edge.

The Frame Sync Input, FSI, can be used if the AD7723 conver-

sion process must be synchronized to an external source. FSI

allows the conversion data presented to the serial interface to be

a filtered and decimated result derived from a known point in

time. A common frame sync signal can be applied to two or

more AD7723s to synchronize them to a common master clock.

When FSI is applied for the first time, the digital filter sequencer

counter is reset to zero, the AD7723 interrupts the current data

transmission, reloads the output shift register, resets SCO and

transmits the conversion result. Synchronization starts immedi-

ately and the following conversions are invalid while the digital

filter settles. FSI can be applied once after power-up, or it can

be a periodic signal, synchronous to CLKIN, occurring every

32 CLKIN cycles. Subsequent FSI inputs applied every 32

CLKIN cycles do not alter the serial data transmission and do

not reset the digital filter sequencer counter. FSI is an optional

signal; if synchronization is not required, FSI can be tied to a

logic low and the AD7723 will generate FSO outputs.

In Serial Mode 1, the control input, SFMT, can be used to

select the format for the serial data transmission (refer to Figure

3). FSO is either a pulse, approximately one SCO cycle in dura-

tion, or a square wave with a period of 32 SCO cycles. With a

logic low level on SFMT, FSO pulses high for one SCO cycle at

the beginning of a data transmission frame. With a logic high

level on SFMT, FSO goes low at the beginning of a data trans-

mission frame and returns high after 16 SCO cycles.

Note that in Serial Mode 1, FSI can be used to synchronize the

AD7723 if SFMT is set to a logic high. If SFMT is set low, the

FSI input will have no effect on synchronization.

In Serial Modes 2 and 3, SFMT should be tied high. TSI and

DOE should be tied low in these modes. The FSO is a pulse,

approximately one SCO cycle in duration, occurring at the

beginning of the serial data transmission.

Two-Channel Multiplexed Operation

Two additional serial interface control pins, DOE and TSI, are

provided to allow the serial data outputs of two AD7723s, to

easily share one serial data line when operating in Serial Mode 1.

Figure 39 shows the connection diagram. Since a serial data

transmission frame lasts 32 SCO cycles, two ADCs can share a

single data line by alternating transmission of their 16-bit out-

put data onto one SDO pin.

AD7723

MASTER

AD7723

SLAVE

FSI

SFMT

TSI

FSI

CLKIN

DOE

CFMT

SDO

SCO

FSO

CLKIN

TSI

CFMT

SFMT

DOE

SDO

SCO

FSO

DVDD

DGND

FROM

CONTROL

LOGIC

TO HOST

PROCESSOR

Figure 39. Serial Mode 1 Connection for Two-Channel

Multiplexed Operation

The Data Output Enable pin, DOE, controls the SDO output

buffer. When the logic level on DOE matches the state of the

TSI pin, the SDO output buffer drives the serial data line, other-

wise the output of the buffer goes high impedance. The serial

format pin, SFMT, is set high to choose the frame sync output

format. The clock format pin, CFMT, is set low so that serial

data is made available on SDO after the rising edge of SCO and

can be latched on the SCO falling edge.

The Master device is selected by setting TSI to a logic low and

connecting its FSO to DOE. The Slave device is selected with

its TSI pin tied high and both its FSI and DOE controlled from

the Master’s FSO. Since the FSO of the Master controls the

DOE input of both the Master and Slave, one ADC’s SDO is

active while the other is high impedance (Figure 40). When the

Master transmits its conversion result during the first 16 SCO

cycles of a data transmission frame, the low level on DOE sets

the slave’s SDO high impedance. Once the Master completes

transmitting its conversion data, its FSO goes high, triggers the

Slave’s FSI to begin its data transmission frame.

Since FSO pulses are gated by the release of FSI (going low)

and the FSI of the Slave device is held high during its data

transmission, the FSO from the Master device must be used for

connection to the host processor.

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