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AD7750 Datasheet(PDF) 14 Page - Analog Devices |
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AD7750 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 16 page ![]() AD7750 –14– REV. 0 Registering the Power Output The low frequency pulse outputs (F1 and F2) of the AD7750 provide the frequency output from the product-to-frequency conversion. These outputs can be used to drive a stepper motor or impulse counter. A high frequency output is available at the pin FOUT. This high frequency output is used for calibration purposes. In Mode 2 the output frequency is 16 × F1(2). With a load current of Ib the frequency at FOUT will be 1.4656 Hz (0.0916 Hz × 16 from calculations). If a higher frequency output is required, the FS pin can be set to VDD 5 V for calibration. In this case the output frequency is equal to 64 × F1 or 5.8624 Hz at Ib—see Table I. NO LOAD THRESHOLD OF THE AD7750 The AD7750 will detect when the power drops below a certain level. When the power (current) drops below a predefined threshold the AD7750 will cease to generate an output drive for the stepper motor (F1, F2). This feature of the AD7750 is intended to reproduce the behavior of Ferraris meters. A Ferraris meter will have friction associated with the wheel rota- tion, therefore the wheel will not rotate below a certain power level. The no load threshold is only implemented in the Magni- tude Only modes (Modes 1, 2, 5 and 6—see Table I). The IEC1036 specification includes a test for this effect by requiring no output pulses during some predetermined time period. This time period is calculated as: time period = 60,000/pulses-per-minute If a meter is calibrated to 100 PPKWHR with a FOUT running 16 times faster than F1 and F2, this time period is 37.5 minutes (60,000/1,600). The IEC1036 specifications state that the no load threshold must be less than the start up current level. This is specified as 0.4% of Ib. The threshold level for a given design can be easily calculated given that the minimum output frequency of the AD7750 is 0.00048% of the maximum output frequency for a full-scale differential dc input. For example if FS = 0, the maximum output frequency for a full-scale dc input is 2.9 Hz (see Table II) and the minimum output frequency is, therefore, 1.39 × 10–5 Hz. Calculating the Threshold Power (Current) The meter used in this example is calibrated to 100 PPKWHR, has an Ib (basic current) of 15 A rms, the line voltage is 220 V rms and the turns ratio of the CT on Channel 1 is 120:1 with an 2 Ω shunt resistor. The nominal voltage on Channel 2 of the AD7750 is 255 mV rms. An FMAX of 6.8 Hz is selected by setting FS = 0. A Magni- tude Only Mode (Mode 2) is selected to enable the no load thresh- old. The gain on Channel 1 is set to 1. The threshold power or current can be found by using the transfer function in Table I. F1, F2 = (1.32 × V 1 × V 2 × Gain × F MAX)/VREF 2 From the transfer function V1 is calculated as 37.95 µV rms— see Calculation 3. This is equivalent to a line current of: (37.95 µV/2 Ω ) × 120 = 2.27 mA rms or 0.5 W or (2.27 mA/15 A) × 100% = 0.015% of Ib. NOTE: The no load threshold as a percentage of Ib will be different for each value of Ib since the no load in watts is fixed: FS = 0, the no load threshold is (FMAX = 6.8 Hz) 0.5 Watts for a 100 PPKWHR meter 5 Watts for a 10 PPKWHR meter FS = 1, the no load threshold is (FMAX = 13.6 Hz) 1 Watt for a 100 PPKWHR meter 10 Watts for a 10 PPKWHR meter Calculation 3 FMIN = 1.32 × V 1 × V 2 × Gain × 6.8 Hz) V REF 2 1.39 × 10–5 Hz = V 1 × 0.2555 × 1 × 6.8)/6.25 V1 = 37.95 µV EXTERNAL LEAD/LAG COMPENSATION External phase compensation is often required in a power meter design to eliminate the phase errors introduced by transducers and external components. The design restriction on any external compensating network is that the network must have an overall low-pass response with a 3 dB point located somewhere between 5 kHz and 6 kHz. The corner frequency of this LPF(s) is much higher than the band of interest. The reason for this is to mini- mize its effect on phase variation at 50 Hz due to component tolerances. With the antialiasing filters on all channels having the same corner (–3 dB) frequency, the main contribution to phase error will be due to the CT. A phase lead in a channel is compensated by lowering the corner frequency of the antialiasing filter to increase its associated lag and therefore cancel the lead. A phase lag in a channel should be compensated by introducing extra lag in the other channel. This can be done as previously described, i.e., moving the corner frequency of the antialiasing filters. The result in this case is that the signal on both channels has the same amount of phase lag and is therefore in phase at the analog inputs to the AD7750. The recommended RC values for the antialiasing filters on the voltage and current channels (see Antialiasing Components Channels 1 and 2) are R = 1 k Ω, C = 33 nF and R = 100 Ω, C = 330 nF respectively. These values produce a phase lag of 0.6 ° through the filters. Varying R in the antialiasing network from 80 Ω to 100 Ω or 800 Ω to 1 kΩ produces a phase variation from 0.475 ° to 0.6° at 50 Hz. This allows the user to vary the lag by 0.125 °. |
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