AD9832 datasheet(9/16 Pages) AD

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AD9832

REV. A

Table V. Commands

Command

0000Write 16 phase bits (Present 8 Bits + 8 Bits

in Defer Register) to Selected PHASE REG.

0001Write 8 phase bits to Defer Register.

0010Write 16 frequency bits (Present 8 Bits

+ 8 Bits in Defer Register) to Selected

FREQ REG.

0011Write 8 frequency bits to Defer Register.

0100Bits D9 (PSEL0) and D10 (PSEL1) are

used to Select the PHASE REG when

SELSRC = 1. When SELSRC = 0, the

PHASE REG is Selected using the pins

PSEL0 and PSEL1.

0101Bit D11 is used to Select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the FREQ REG is Selected using the pin

FSELECT.

0110To control the PSEL0, PSEL1 and

FSELECT bits using only one write, this

command is used. Bits D9 and D10 are

used to Select the PHASE REG and Bit

11 is used to Select the FREQ REG when

SELSRC = 1. When SELSRC = 0, the

PHASE REG is Selected using the pins

PSEL0 and PSEL1 and the FREQ REG

is Selected using the pin FSELECT.

0111Reserved. Configures the AD9832 for

Test Purposes.

Table VI. Controlling the AD9832

D15 D14 Command

Selects source of Control for the PHASE and FREQ

Registers and Enables Synchronization.

Bit D13 is the SYNC Bit. When this bit is High,

reading of the FSELECT, PSEL0 and PSEL1 bits/

pins and the loading of the Destination Register with

data is synchronized with the rising edge of MCLK.

The latency is increased by 2 MCLK cycles when

SYNC = 1. When SYNC = 0, the loading of the

data and the sampling of FSELECT/PSEL0/PSEL1

occurs asynchronously.

Bit D12 is the Select Source Bit (SELSRC). When

this bit Equals 1, the PHASE/FREQ REG is

Selected using the bits FSELECT, PSEL0 and

PSEL1. When SELSRC = 0, the PHASE/FREQ

REG is Selected using the pins FSELECT, PSEL0

and PSEL1.

Sleep, Reset and Clear.

D13 is the SLEEP bit. When this bit equals 1, the

AD9832 is powered down, internal clocks are

disabled and the DAC’s current sources and

REFOUT are turned off. When SLEEP = 0, the

AD9832 is powered up. When RESET (D12) = 1,

the phase accumulator is set to zero phase which

corresponds to an analog output of midscale. When

CLR (D11) = 1, SYNC and SELSRC are set to

zero. CLR resets to 0 automatically.

Table VII. Writing to the AD9832 Data Registers

Table VIII. Setting SYNC and SELSRC

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Table IX. Power-Down, Resetting and Clearing the AD9832

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