AD9832

–14–

REV. A

AD9832 to 68HC11/68L11 Interface

Figure 27 shows the serial interface between the AD9832 and

the 68HC11/68L11 microcontroller. The microcontroller is

configured as the master by setting bit MSTR in the SPCR to 1

and this provides a serial clock on SCK while the MOSI output

drives the serial data line SDATA. Since the microcontroller

does not have a dedicated frame sync pin, the FSYNC signal is

derived from a port line (PC7). The set-up conditions for cor-

rect operation of the interface are as follows: the SCK idles high

between write operations (CPOL = 0), data is valid on the SCK

falling edge (CPHA = 1). When data is being transmitted to the

AD9832, the FSYNC line is taken low (PC7). Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with

only 8 falling clock edges occurring in the transmit cycle. Data

is transmitted MSB first. In order to load data into the AD9832,

PC7 is held low after the first 8 bits are transferred and a second

serial write operation is performed to the AD9832. Only after

the second 8 bits have been transferred should FSYNC be taken

high again.

68HC11/68L11

AD9832

PC7

MOSI

SCK

SDATA

SCLK

FSYNC

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 27. 68HC11/68L11 to AD9832 Interface

AD9832 to 80C51/80L51 Interface

Figure 28 shows the serial interface between the AD9832 and

the 80C51/80L51 microcontroller. The microcontroller is oper-

ated in Mode 0 so that TXD of the 80C51/80L51 drives SCLK

of the AD9832 while RXD drives the serial data line SDATA.

The FSYNC signal is again derived from a bit programmable

pin on the port (P3.3 being used in the diagram). When data is

to be transmitted to the AD9832, P3.3 is taken low. The

80C51/80L51 transmits data in 8-bit bytes thus, only 8 falling

SCLK edges occur in each cycle. To load the remaining 8 bits

to the AD9832, P3.3 is held low after the first 8 bits have been

transmitted and a second write operation is initiated to transmit

the second byte of data. P3.3 is taken high following the comple-

tion of the second write operation. SCLK should idle high

between the two write operations. The 80C51/80L51 outputs

the serial data in a format which has the LSB first. The AD9832

accepts the MSB first (the 4 MSBs being the control informa-

tion, the next 4 bits being the address while the 8 LSBs contain

the data when writing to a destination register). Therefore, the

transmit routine of the 80C51/80L51 must take this into ac-

count and rearrange the bits so that the MSB is output first.

80C51/80L51

AD9832

P3.3

RXD

TXD

SDATA

SCLK

FSYNC

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 28. 80C51/80L51 to AD9832 Interface

AD9832 to DSP56002 Interface

Figure 29 shows the interface between the AD9832 and the

DSP56002. The DSP56002 is configured for normal mode

asynchronous operation with a gated internal clock (SYN = 0,

GCK = 1, SCKD = 1). The frame sync pin is generated inter-

nally (SC2 = 1), the transfers are 16-bits wide (WL1 = 1, WL0

= 0) and the frame sync signal will frame the 16 bits (FSL = 0).

The frame sync signal is available on Pin SC2, but it needs to be

inverted before being applied to the AD9832. The interface to

the DSP56000/DSP56001 is similar to that of the DSP56002.

DSP56002

AD9832

SC2

STD

SCK

SDATA

SCLK

FSYNC

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 29. AD9832 to DSP56002 Interface

AD9832 Evaluation Board

The AD9832 Evaluation Board allows designers to evaluate the

high performance AD9832 DDS modulator with a minimum of

effort.

To prove that this device will meet the user’s waveform synthe-

sis requirements, the user requires only a 3.3 V or 5 V power

supply, an IBM-compatible PC and a spectrum analyzer along

with the evaluation board. The evaluation board setup is shown

below.

The DDS evaluation kit includes a populated, tested AD9832

printed circuit board, along with the software that controls the

AD9832, in a Windows environment.

AD9832.EXE

IBM-COMPATIBLE PC

PARALLEL PORT

CENTRONICS

PRINTER CABLE

AD9832 EVALUATION

BOARD

Figure 30. AD9832 Evaluation Board Setup