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ADF4106 Datasheet(PDF) 11 Page - Analog Devices

Part # ADF4106
Description  PLL Frequency Synthesizer
PDF  20 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4106 Datasheet(HTML) 11 Page - Analog Devices

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REV. 0
ADF4106
–11–
Table III. Reference Counter Latch Map
LDP
OPERATION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION
ABP2
ABP1
ANTIBACKLASH PULSEWIDTH
0
0
2.9ns
0
1
1.3ns
1
0
6.0ns
1
1
2.9ns
R14
R13
R12
..........
R3
R2
R1
DIVIDE RATIO
0
0
0
..........
0011
0
0
0
..........
0102
0
0
0
..........
0113
0
0
0
..........
1004
.
.
.
..........
....
.
.
.
..........
....
.
.
.
..........
....
1
1
1
..........
1
0
0
16380
1
1
1
..........
1
0
1
16381
1
1
1
..........
1
1
0
16382
1
1
1
..........
1
1
1
16383
X = DON’T CARE
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (0)
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
T1
T2
LDP
CONTROL
BITS
14-BIT REFERENCE COUNTER
TEST
MODE BITS
DB21
DB22
DB23
0
0
ANTI-
BACKLASH
WIDTH
X
RESERVED



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