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ADF4110 Datasheet(PDF) 13 Page - Analog Devices

Part # ADF4110
Description  RF PLL Frequency Synthesizers
PDF  24 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4110 Datasheet(HTML) 13 Page - Analog Devices

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REV. 0
ADF4110/ADF4111/ADF4112/ADF4113
–13–
Table III. Reference Counter Latch Map
OPERATION
LDP
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
0
1
TEST MODE BITS SHOULD
BE SET TO 00 FOR NORMAL
OPERATION
R14
0
0
0
0
•
•
•
1
1
1
1
R13
0
0
0
0
•
•
•
1
1
1
1
R12
0
0
0
0
•
•
•
1
1
1
1
R3
0
0
0
1
•
•
•
1
1
1
1
R2
0
1
1
0
•
•
•
0
0
1
1
R1
1
0
1
0
•
•
•
0
1
0
1
DIVIDE RATIO
1
2
3
4
•
•
•
16380
16381
16382
16383
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
••••••••••
TEST
MODE BITS
DB23 DB22
DB21 DB20
DB19 DB18
DB17 DB16
DB15 DB14
DB12
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB13
LDP
T2
T1
R14
R13
R12
R11
R10
R8
R7
R6
R5
R4
R3
R2
R1
C2 (0) C1 (0)
R9
14-BIT REFERENCE COUNTER
CONTROL
BITS
DB2
DB1
DB0
SYNC
DLY
ABP2 ABP1
ANTI-
BACKLASH
WIDTH
SYNC
DLY
ABP1
ABP2
0
0
1
1
0
1
0
1
3.0ns
1.5ns
6.0ns
3.0ns
ANTIBACKLASH PULSEWIDTH
SYNC
DLY
0
0
1
1
0
1
0
1
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH NONDELAYED VERSION OF RF INPUT
NORMAL OPERATION
OUTPUT OF PRESCALER IS RESYNCHRONIZED
WITH DELAYED VERSION OF RF INPUT
OPERATION
X
X = DON'T
CARE



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