ADG714 datasheet(5/16 Pages) AD

Part #	ADG714

Description	CMOS, Low Voltage Serially-Controlled, Octal SPST Switches

PDF	16 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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5 / 16 page

ADG714/ADG715

–5–

REV. 0

ADG714 TIMING CHARACTERISTICS1, 2

Parameter

Limit at TMIN, TMAX

Unit

Conditions/Comments

fSCLK

MHz max

SCLK Cycle Frequency

ns min

SCLK Cycle Time

ns min

SCLK High Time

ns min

SCLK Low Time

ns min

SYNC to SCLK Rising Edge Setup Time

ns min

Data Setup Time

4.5

ns min

Data Hold Time

ns min

SCLK Falling Edge to

SYNC Rising Edge

ns min

Minimum

SYNC High Time

ns min

SCLK Rising Edge to DOUT Valid

NOTES

1See Figure 1.

2All input signals are speciﬁed with tr = tf = 5 ns (10% to 90% of V

DD) and timed from a voltage level of (VIL + VIH)/2.

L = 20 pF, RL = 1 k

Ω.

Speciﬁcations subject to change without notice.

SCLK

SYNC

DIN

DOUT

DB0

DB7

DB71

DB61

DB21

DB11

DB01

NOTE

1DATA FROM PREVIOUS WRITE CYCLE

Figure 1. 3-Wire Serial Interface Timing Diagram

(VDD = 2.7 V to 5.5 V. All speciﬁcations –40 C to +85 C unless otherwise noted.)

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