ADSP-2173 datasheet(7/52 Pages) AD

7 / 52 page

ADSP-2171/ADSP-2172/ADSP-2173

REV. A

–7–

Figure 3. ADSP-217x Basic System Configuration

Because the ADSP-217x includes an on-chip oscillator circuit,

an external crystal may be used. The crystal should be con-

nected across the CLKIN and XTAL pins, with two capacitors

connected as shown in Figure 4. A parallel-resonant, fundamen-

tal frequency, microprocessor-grade crystal should be used.

CLKIN

CLKOUT

XTAL

ADSP-217x

Figure 4. External Crystal Connections

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This can be enabled and disabled

by the CLKODIS bit in the SPORT0 Autobuffer Control Reg-

ister, DM[0x3FF3].

Reset

The RESET signal initiates a master reset of the ADSP-217x.

The RESET signal must be asserted during the power-up se-

quence to assure proper initialization. RESET during initial

power-up must be held long enough to allow the internal clock

SCLK

RFS

TFS

ADSP-217x

CLKIN

CLKOUT

SERIAL

PORT 0

GND

SERIAL

PORT 1

DATA

ADDRESS

PMS

DMS

BMS

SERIAL DEVICE

XTAL

MMAP

IRQ2

RESET

SCLK

RFS or IRQ0

TFS or IRQ1

DT or FO

DR or FI

DATA MEMORY

PERIPHERALS

PROGRAM

MEMORY

(OPTIONAL)

NOTE:

THE TWO MSBs OF THE DATA BUS ARE USED AS THE MSBs OF THE BOOT EPROM ADDRESS.

THIS IS ONLY REQUIRED FOR THE 27C256 AND 27C512.

BOOT MEMORY

SERIAL DEVICE

(OPTIONAL)

15-8

e.g., EPROM

27C64

27C128

27C256

27C512

HOST

MODE

FL2-0

HOST

PROCESSOR

(OPTIONAL)

HIP CONTROL

HIP

HIP DATA/ADDR

PWDACK

PWD

CLOCK OR

CRYSTAL

23-22

23-8

(OPTIONAL)

to stabilize. If RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid VDD is ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 CLKIN cycles ensures that the PLL has locked but does

not include the crystal oscillator start-up time. During this

power-up sequence the RESET signal should be held low. On

any subsequent resets, the RESET signal must meet the mini-

mum pulse width specification, tRSP.

The RESET input contains some hysteresis; however, if you use

an RC circuit to generate your RESET signal, the use of an ex-

ternal Schmidt trigger is recommended.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT reg-

ister. When RESET is released, if there is no pending bus re-

quest and the chip is configured for booting (MMAP = 0), the

boot-loading sequence is performed. Then the first instruction is

fetched from internal program memory location 0x0000.

ADSP-2173 Datasheet(PDF) 7 Page - Analog Devices

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