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ADSP-2173 Datasheet(PDF) 13 Page - Analog Devices |
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ADSP-2173 Datasheet(HTML) 13 Page - Analog Devices |
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13 / 52 page ![]() ADSP-2171/ADSP-2172/ADSP-2173 REV. A –13– Control Registers SPORT0 SCLKDIV Serial Clock Divide Modulus 0x3FF5 SPORT0 RFSDIV Receive Frame Sync Divide Modulus 0x3FF4 15 14 13 12 11 10 9 8765 4321 0 15 14 13 12 11 10 9 8765 4321 0 SPORT0 Autobuffer Control Register 0x3FF3 15 14 13 12 11 10 9 8765 4321 0 0 0 0 00 0 RBUF Receive Autobuffering Enable TBUF Transmit Autobuffering Enable RMREG Receive Autobuffer M Register RIREG Receive Autobuffer I Register CLKODIS CLKOUT Disable Control Bit BIASRND MAC Biased Rounding Control Bit TIREG Transmit Autobuffer I Register TMREG Transmit Autobuffer M Register SPORT1 Control Register 0x3FF2 Flag Out (Read Only) Internal Serial Clock Generation ISCLK Receive Frame Sync Required RFSR Receive Frame Sync Width RFSW Transmit Frame Sync Required TFSR Transmit Frame Sync Width TFSW SLEN Serial Word Length DTYPE Data Format 00 = right justify, zero-fill unused MSBs 01 = right justify, sign extend into unused MSBs 10 = compand using µ-law 11 = compand using A-law INVRFS Invert Receive Frame Sync INVTFS Invert Transmit Frame Sync IRFS Internal Receive Frame Sync Enable ITFS Internal Transmit Frame Sync Enable 15 14 13 12 11 10 9 8765 4321 0 0 0 0 0 0 0 00 00 0 0 0 0 0 |
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