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ADSP-2173 Datasheet(PDF) 21 Page - Analog Devices

Part # ADSP-2173
Description  DSP Microcomputer
PDF  52 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-2173 Datasheet(HTML) 21 Page - Analog Devices

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ADSP-2171/ADSP-2172/ADSP-2173
REV. A
–21–
ADSP-2171/ADSP-2172
Parameter
Min
Max
Unit
Bus Request/Grant
Timing Requirement:
tBH
BR
Hold after CLKOUT High
1
0.25tCK + 2
ns
tBS
BR
Setup before CLKOUT Low
1
0.25tCK + 17
ns
Switching Characteristic:
tSD
CLKOUT High to DMS, PMS, BMS,
0.25tCK + 16
ns
RD
, WR Disable
tSDB
DMS
, PMS, BMS, RD, WR
Disable to BG Low
0
ns
tSE
BG
High to DMS, PMS, BMS,
RD
, WR Enable
0
ns
tSEC
DMS
, PMS, BMS, RD, WR
Enable to CLKOUT High
0.25tCK – 7
ns
tSDBH
DMS
, PMS, BMS, RD, WR
Disable to BGH Low
2
0ns
tSEH
BGH
High to DMS, PMS, BMS,
RD
, WR Enable
2
0ns
NOTES
1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
t
BS
BR
t
BH
CLKOUT
PMS, DMS
BMS, RD
WR
BG
CLKOUT
t
SD
t
SDB
t
SE
t
SEC
tSDBH
BGH
tSEH
Figure 10. Bus Request–Bus Grant



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