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ADV7175A Datasheet(PDF) 18 Page - Analog Devices |
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ADV7175A Datasheet(HTML) 18 Page - Analog Devices |
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18 / 52 page ![]() ADV7175A/ADV7176A –18– REV. B FIELD PIXEL DATA PAL = 12 * CLOCK/2 NTSC = 16 * CLOCK/2 PAL = 132 * CLOCK/2 NTSC = 122 * CLOCK/2 Cb Y Cr Y HSYNC BLANK Figure 20. Timing Mode 1 Odd/Even Field Transitions Master/Slave Mode 2: Slave Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 0 ) In this mode the ADV7175A/ADV7176A accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). 522 523 524 525 12 34 5 678 9 10 11 20 21 22 DISPLAY DISPLAY VERTICAL BLANK ODD FIELD EVEN FIELD HSYNC BLANK VSYNC 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285 ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK HSYNC BLANK VSYNC Figure 21. Timing Mode 2 (NTSC) |
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