ADV7175A datasheet(24/52 Pages) AD

24 / 52 page

ADV7175A/ADV7176A

–24–

REV. B

MODE REGISTER 1 MR1 (MR17–MR10)

(Address (SR4–SR0) = 01H)

Figure 33 shows the various operations under the control of Mode

MR1 BIT DESCRIPTION

Interlaced Mode Control (MR10)

This bit is used to set up the output to interlaced or noninter-

laced mode. This mode is only relevant when the part is in

composite video mode.

Closed Captioning Field Control (MR12–MR11)

These bits control the fields on which closed captioning data is

displayed; closed captioning information can be displayed on an

odd field, even field or both fields.

DAC Control (MR16–MR13)

These bits can be used to power down the DACs. This can

be used to reduce the power consumption of the ADV7175A/

ADV7176A if any of the DACs are not required in the application.

Color Bar Control (MR17)

This bit can be used to generate and output an internal color

bar test pattern. The color bar configuration is 75/7.5/75/7.5

for NTSC and 100/0/75/0 for PAL. It is important to note that

when color bars are enabled the ADV7175A/ADV7176A is

configured in a master timing mode as per the one selected by

bits TR01 and TR02.

SUBCARRIER FREQUENCY REGISTER 3-0

(FSC3–FSC0)

(Address [SR4–SR0] = 05H–02H)

These 8-bit wide registers are used to set up the subcarrier fre-

quency. The value of these registers are calculated by using the

following equation:

Subcarrier Frequency Register =

232 –1

FCLK

× F

SCF

i.e.: NTSC Mode,

FCLK = 27 MHz,

FSCF = 3.5795454 MHz

Subcarrier Frequency Value =

232 –1

×106

× 3.5795454 ×106

= 21F07C16 HEX

Figure 34 shows how the frequency is set up by the four registers.

SUBCARRIER

FREQUENCY

REG 3

SUBCARRIER

FREQUENCY

REG 2

SUBCARRIER

FREQUENCY

REG 1

SUBCARRIER

FREQUENCY

REG 0

FSC30

FSC29

FSC27

FSC25

FSC28

FSC24

FSC31

FSC26

FSC22

FSC21

FSC19

FSC17

FSC20

FSC16

FSC23

FSC18

FSC14

FSC13

FSC11

FSC9

FSC12

FSC8

FSC15

FSC10

FSC6

FSC5

FSC3

FSC1

FSC4

FSC0

FSC7

FSC2

Figure 34. Subcarrier Frequency Register

SUBCARRIER PHASE REGISTER (FP7–FP0)

(Address [SR4–SR0] = 06H)

This 8-bit wide register is used to set up the subcarrier phase.

Each bit represents 1.41

°.

TIMING REGISTER 0 (TR07–TR00)

(Address [SR4–SR0] = 07H)

Figure 35 shows the various operations under the control of

Timing Register 0. This register can be read from as well as

written to. This register can be used to adjust the width and

position of the master mode timing signals.

TR0 BIT DESCRIPTION

Master/Slave Control (TR00)

This bit controls whether the ADV7175A/ADV7176A is in

master or slave mode.

Timing Mode Control (TR02–TR01)

These bits control the timing mode of the ADV7175A/

ADV7176A. These modes are described in the Timing and

Control section of the data sheet.

BLANK Control (TR03)

This bit controls whether the

BLANK input is used when the

part is in slave mode.

Luma Delay Control (TR05–TR04)

These bits control the addition of a luminance delay. Each bit

represents a delay of 74 ns.

Pixel Port Select (TR06)

This bit is used to set the pixel port to accept 8-bit or 16-bit

data. If an 8-bit input is selected the data will be set up on Pins

P7–P0.

Timing Register Reset (TR07)

Toggling TR07 from low to high and low again resets the inter-

nal timing counters. This bit should be toggled after power-up,

reset or changing to a new timing mode.

TR01

TR00

TR07

TR02

TR03

TR05

TR06

TR04

TIMING

TR07

BLACK INPUT

CONTROL

ENABLE

DISABLE

TR03

PIXEL PORT

CONTROL

8-BIT

16-BIT

TR06

MASTER/SLAVE

CONTROL

SLAVE TIMING

MASTER TIMING

TR00

LUMA DELAY

0ns DELAY

74ns DELAY

148ns DELAY

222ns DELAY

TR05 TR04

TIMING MODE

SELECTION

MODE 0

MODE 1

MODE 2

MODE 3

TR02 TR01

Figure 35. Timing Register 0

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