ADV7175A datasheet(21/52 Pages) AD

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ADV7175A/ADV7176A

–21–

REV. B

OUTPUT VIDEO TIMING

The video timing generator generates the appropriate SYNC,

BLANK and BURST sequence that controls the output analog

waveforms. These sequences are summarized below. In slave

modes, the following sequences are synchronized with the input

timing control signals. In master modes, the timing generator

free runs and generates the following sequences in addition to

the output timing control signals.

NTSC–Interlaced: Scan Lines 1–9 and 264–272 are always

blanked and vertical sync pulses are included. Scan Lines 525,

10–21 and 262, 263, 273–284 are also blanked and can be used

for closed captioning data. Burst is disabled on lines 1–6, 261–

269 and 523–525.

NTSC–Noninterlaced: Scan Lines 1–9 are always blanked,

and vertical sync pulses are included. Scan Lines 10–21 are also

blanked and can be used for closed captioning data. Burst is

disabled on Lines 1–6, 261–262.

PAL–Interlaced: Scan Lines 1–6, 311–318 and 624–625 are

always blanked, and vertical sync pulses are included in Fields

1, 2, 5 and 6. Scan Lines 1–5, 311–319 and 624–625 are al-

ways blanked, and vertical sync pulses are included in Fields 3,

4, 7 and 8. The remaining scan lines in the vertical blanking

interval are also blanked and can be used for teletext data.

Burst is disabled on Lines 1–6, 311–318 and 623–625 in Fields

1, 2, 5 and 6. Burst is disabled on Lines 1–5, 311–319 and

623–625 in Fields 3, 4, 7 and 8.

PAL–Noninterlaced: Scan Lines 1–6 and 311–312 are always

blanked, and vertical sync pulses are included. The remaining

scan lines in the vertical blanking interval are also blanked and

can be used for teletext data. Burst is disabled on Lines 1–5,

310–312.

POWER-ON RESET

After power-up, it is necessary to execute a reset operation. A

reset occurs on the falling edge of a high-to-low transition on

the

RESET pin. This initializes the pixel port so that the

pixel inputs, P7–P0 are selected. After reset, the ADV7175A/

ADV7176A is automatically set up to operate in NTSC mode.

Subcarrier frequency code 21F07C16HEX is loaded into the

subcarrier frequency registers. All other registers, with the

exception of Mode Register 0, are set to 00H. All bits in Mode

MR02 of Mode Register 0 is set to Logic “1.” This enables the

7.5 IRE pedestal.

SCH Phase Mode

The SCH phase is configured in default mode to reset every

four (NTSC) or eight (PAL) fields to avoid an accumulation of

SCH phase error over time. In an ideal system, zero SCH phase

error would be maintained forever, but in reality, this is impos-

sible to achieve due to clock frequency variations. This effect is

reduced by the use of a 32-bit DDS, which generates this SCH.

Resetting the SCH phase every four or eight fields avoids the

accumulation of SCH phase error, and results in very minor

SCH phase jumps at the start of the four or eight field sequence.

Resetting the SCH phase should not be done if the video source

does not have stable timing or the ADV7175A/ADV7176A is

configured in RTC mode (MR21 = 1 and MR22 = 1). Under

these conditions (unstable video) the subcarrier phase reset

should be enabled MR22 = 0 and MR21 = 1) but no reset

applied. In this configuration the SCH phase will never be reset,

which means that the output video will now track the unstable

input video. The subcarrier phase reset, when applied, will reset

the SCH phase to Field 0 at the start of the next field (e.g.,

subcarrier phase reset applied in Field 5 [PAL] on the start of

the next field SCH phase will be reset to Field 0).

MPU PORT DESCRIPTION

The ADV7175A and ADV7176A support a two-wire serial (I

Compatible) microprocessor bus driving multiple peripherals.

Two inputs, serial data (SDATA) and serial clock (SCLOCK),

carry information between any device connected to the bus.

Each slave device is recognized by a unique address. The

ADV7175A and ADV7176A each have four possible slave

addresses for both read and write operations. These are unique

addresses for each device and are illustrated in Figure 27 and

Figure 28. The LSB sets either a read or write operation. Logic

Level “1” corresponds to a read operation, while Logic Level

“0” corresponds to a write operation. A1 is set by setting the

ALSB pin of the ADV7175A/ADV7176A to Logic Level “0” or

Logic Level “1.”

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

WRITE

READ

Figure 27. ADV7175A Slave Address

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

WRITE

READ

Figure 28. ADV7176A Slave Address

To control the various devices on the bus, the following proto-

col must be followed: First, the master initiates a data transfer by

establishing a start condition, defined by a high-to-low transition

on SDATA while SCLOCK remains high. This indicates that

an address/data stream will follow. All peripherals respond to

the start condition and shift the next eight bits (7-bit address +

W bit). The bits transfer from MSB down to LSB. The pe-

ripheral that recognizes the transmitted address responds by

pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition is where the device monitors the SDATA and SCLOCK

lines waiting for the start condition and the correct transmitted

address. The R/

W bit determines the direction of the data. A

Logic “0” on the LSB of the first byte means that the master

will write information to the peripheral. A Logic “1” on the

LSB of the first byte means that the master will read informa-

tion from the peripheral.

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